Fully planarized four-level interconnection with stacked vias using CMP of selective CVD-Al and insulator and its application to quarter micron gate array LSIs

T. Amazawa, E. Yamamoto, K. Sakuma, Y. Ito, K. Kamoshida, K. Ikeda, K. Saito, H. Ishii, S. Kato, S. Yagi, K. Hiraoka, T. Ueki, T. Takeda, Y. Arita

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2 Citations (Scopus)

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Physics & Astronomy

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