Fully-parallel VLSI implementation of vector quantization processor using neuron-MOS technology

Akira Nakada, Masahiro Konda, Tatsuo Morimoto, Takemi Yonezawa, Tadashi Shibata, Tadahiro Ohmi

    Research output: Contribution to journalArticle

    7 Citations (Scopus)

    Abstract

    An analog vector quantization processor has been designed based on the neuron-MOS (νMOS) technology. In order to achieve a high integrating density, template information is merged into the matching cell (the absolute value circuitry) using the νMOS ROM technology. A new-architecture νMOS winner-take-all (WTA) circuit is employed for fully-parallel search for the minimum-distance vector. The WTA performs multi-resolution winner search with an automatic feedback gain control. A test chip having 256 16-element fixed template vectors has been built in a 1.5-μm double-polysilicon CMOS technology with the chip size of 7.2 mm × 7.2 mm, and the basic operation of the circuits has been demonstrated.

    Original languageEnglish
    Pages (from-to)1730-1737
    Number of pages8
    JournalIEICE Transactions on Electronics
    VolumeE82-C
    Issue number9
    Publication statusPublished - 1999 Jan 1

    Keywords

    • Analog LSI
    • Image compression
    • Neuron MOS
    • Vector quantization
    • Winner-take-all

    ASJC Scopus subject areas

    • Electronic, Optical and Magnetic Materials
    • Electrical and Electronic Engineering

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  • Cite this

    Nakada, A., Konda, M., Morimoto, T., Yonezawa, T., Shibata, T., & Ohmi, T. (1999). Fully-parallel VLSI implementation of vector quantization processor using neuron-MOS technology. IEICE Transactions on Electronics, E82-C(9), 1730-1737.