Fully-filled, highly-reliable fine-pitch interposers with TSV aspect ratio >10 for future 3D-LSI/IC packaging

Murugesan Murugesan, Takafumi Fukushima, Kiyoharu Mori, Ai Nakamura, Yisang Lee, Makoto Motoyoshi, J. C. Bea, Shigeru Watariguchi, Mitsumasa Koyanagi

Research output: Chapter in Book/Report/Conference proceedingConference contribution

5 Citations (Scopus)

Abstract

Si interposer with 10 μm-width, 100 μm-deep through-silicon via (TSV) has been fabricated using electroless (EL) Ni as barrier and seed layers, and characterized for their electrical resistance. The chemistry of electroless-Ni plating bath was meticulously adjusted for the conformal formation of Ni along the TSV side wall. From the resistance value of 36 ΩW per TSV obtained from the Kelvin measurement of these Cu-TSV chain showed that the electroless Ni layer well acts as a good seed layer for completely filling the high aspect ratio TSVs by Cu-electroplating.

Original languageEnglish
Title of host publicationProceedings - IEEE 69th Electronic Components and Technology Conference, ECTC 2019
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages1047-1051
Number of pages5
ISBN (Electronic)9781728114989
DOIs
Publication statusPublished - 2019 May
Externally publishedYes
Event69th IEEE Electronic Components and Technology Conference, ECTC 2019 - Las Vegas, United States
Duration: 2019 May 282019 May 31

Publication series

NameProceedings - Electronic Components and Technology Conference
Volume2019-May
ISSN (Print)0569-5503

Conference

Conference69th IEEE Electronic Components and Technology Conference, ECTC 2019
CountryUnited States
CityLas Vegas
Period19/5/2819/5/31

Keywords

  • Barrier/seed laer
  • Cu-TSV
  • Cu-diffusion
  • Electroless Ni
  • Si interposer

ASJC Scopus subject areas

  • Electronic, Optical and Magnetic Materials
  • Electrical and Electronic Engineering

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