FPGA implementation of binarized perceptron learning hardware using CMOS invertible logic

Duckgyu Shin; Naoya Onizawa; Takahiro Hanyu

doi:10.1109/ICECS46596.2019.8965097

FPGA implementation of binarized perceptron learning hardware using CMOS invertible logic

Duckgyu Shin, Naoya Onizawa, Takahiro Hanyu

Systems & Software Division

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Abstract

This paper introduces FPGA implementation of learning hardware for a neural network. The proposed learning hardware is designed using CMOS invertible logic that realizes probabilistic bidirectional (forward and backward) operations with basic CMOS logic gates. The backward operation based on CMOS invertible logic makes hardware-based learning possible because the loss function is not required. For a simple case study, the proposed learning hardware trains using simplified a MNIST data set for a 25-input binarized perceptron. Our FPGA implementation on Digilent Genesys 2 achieves around 100 x faster operating speed than that using a traditional learning algorithm on software while maintaining the same recognition accuracy of 99%.

Original language	English
Title of host publication	2019 26th IEEE International Conference on Electronics, Circuits and Systems, ICECS 2019
Publisher	Institute of Electrical and Electronics Engineers Inc.
Pages	115-116
Number of pages	2
ISBN (Electronic)	9781728109961
DOIs	https://doi.org/10.1109/ICECS46596.2019.8965097
Publication status	Published - 2019 Nov
Event	26th IEEE International Conference on Electronics, Circuits and Systems, ICECS 2019 - Genoa, Italy Duration: 2019 Nov 27 → 2019 Nov 29

Publication series

Name	2019 26th IEEE International Conference on Electronics, Circuits and Systems, ICECS 2019

Conference

Conference	26th IEEE International Conference on Electronics, Circuits and Systems, ICECS 2019
Country	Italy
City	Genoa
Period	19/11/27 → 19/11/29

Keywords

Hamiltonian
Spin gate
Stochastic computing

ASJC Scopus subject areas

Electrical and Electronic Engineering
Control and Optimization
Computer Networks and Communications
Hardware and Architecture

Access to Document

10.1109/ICECS46596.2019.8965097

Fingerprint Dive into the research topics of 'FPGA implementation of binarized perceptron learning hardware using CMOS invertible logic'. Together they form a unique fingerprint.

Cite this

Shin, D., Onizawa, N., & Hanyu, T. (2019). FPGA implementation of binarized perceptron learning hardware using CMOS invertible logic. In 2019 26th IEEE International Conference on Electronics, Circuits and Systems, ICECS 2019 (pp. 115-116). [8965097] (2019 26th IEEE International Conference on Electronics, Circuits and Systems, ICECS 2019). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/ICECS46596.2019.8965097

FPGA implementation of binarized perceptron learning hardware using CMOS invertible logic. / Shin, Duckgyu; Onizawa, Naoya ; Hanyu, Takahiro.

2019 26th IEEE International Conference on Electronics, Circuits and Systems, ICECS 2019. Institute of Electrical and Electronics Engineers Inc., 2019. p. 115-116 8965097 (2019 26th IEEE International Conference on Electronics, Circuits and Systems, ICECS 2019).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Shin, D, Onizawa, N & Hanyu, T 2019, FPGA implementation of binarized perceptron learning hardware using CMOS invertible logic. in 2019 26th IEEE International Conference on Electronics, Circuits and Systems, ICECS 2019., 8965097, 2019 26th IEEE International Conference on Electronics, Circuits and Systems, ICECS 2019, Institute of Electrical and Electronics Engineers Inc., pp. 115-116, 26th IEEE International Conference on Electronics, Circuits and Systems, ICECS 2019, Genoa, Italy, 19/11/27. https://doi.org/10.1109/ICECS46596.2019.8965097

Shin D, Onizawa N , Hanyu T. FPGA implementation of binarized perceptron learning hardware using CMOS invertible logic. In 2019 26th IEEE International Conference on Electronics, Circuits and Systems, ICECS 2019. Institute of Electrical and Electronics Engineers Inc. 2019. p. 115-116. 8965097. (2019 26th IEEE International Conference on Electronics, Circuits and Systems, ICECS 2019). https://doi.org/10.1109/ICECS46596.2019.8965097

Shin, Duckgyu ; Onizawa, Naoya ; Hanyu, Takahiro. / FPGA implementation of binarized perceptron learning hardware using CMOS invertible logic. 2019 26th IEEE International Conference on Electronics, Circuits and Systems, ICECS 2019. Institute of Electrical and Electronics Engineers Inc., 2019. pp. 115-116 (2019 26th IEEE International Conference on Electronics, Circuits and Systems, ICECS 2019).

@inproceedings{16282a11817f45269898fa45e4c97614,

title = "FPGA implementation of binarized perceptron learning hardware using CMOS invertible logic",

abstract = "This paper introduces FPGA implementation of learning hardware for a neural network. The proposed learning hardware is designed using CMOS invertible logic that realizes probabilistic bidirectional (forward and backward) operations with basic CMOS logic gates. The backward operation based on CMOS invertible logic makes hardware-based learning possible because the loss function is not required. For a simple case study, the proposed learning hardware trains using simplified a MNIST data set for a 25-input binarized perceptron. Our FPGA implementation on Digilent Genesys 2 achieves around 100 x faster operating speed than that using a traditional learning algorithm on software while maintaining the same recognition accuracy of 99%.",

keywords = "Hamiltonian, Spin gate, Stochastic computing",

author = "Duckgyu Shin and Naoya Onizawa and Takahiro Hanyu",

note = "Funding Information: ACKNOWLEDGMENT This work was supported in part by JST PRESTO Grant Number JPMJPR18M5, MEXT Brainware LSI Project and the WISE Program for AI Electronics, Tohoku University.; 26th IEEE International Conference on Electronics, Circuits and Systems, ICECS 2019 ; Conference date: 27-11-2019 Through 29-11-2019",

year = "2019",

month = nov,

doi = "10.1109/ICECS46596.2019.8965097",

language = "English",

series = "2019 26th IEEE International Conference on Electronics, Circuits and Systems, ICECS 2019",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

pages = "115--116",

booktitle = "2019 26th IEEE International Conference on Electronics, Circuits and Systems, ICECS 2019",

}

TY - GEN

T1 - FPGA implementation of binarized perceptron learning hardware using CMOS invertible logic

AU - Shin, Duckgyu

AU - Onizawa, Naoya

AU - Hanyu, Takahiro

N1 - Funding Information: ACKNOWLEDGMENT This work was supported in part by JST PRESTO Grant Number JPMJPR18M5, MEXT Brainware LSI Project and the WISE Program for AI Electronics, Tohoku University.

PY - 2019/11

Y1 - 2019/11

N2 - This paper introduces FPGA implementation of learning hardware for a neural network. The proposed learning hardware is designed using CMOS invertible logic that realizes probabilistic bidirectional (forward and backward) operations with basic CMOS logic gates. The backward operation based on CMOS invertible logic makes hardware-based learning possible because the loss function is not required. For a simple case study, the proposed learning hardware trains using simplified a MNIST data set for a 25-input binarized perceptron. Our FPGA implementation on Digilent Genesys 2 achieves around 100 x faster operating speed than that using a traditional learning algorithm on software while maintaining the same recognition accuracy of 99%.

AB - This paper introduces FPGA implementation of learning hardware for a neural network. The proposed learning hardware is designed using CMOS invertible logic that realizes probabilistic bidirectional (forward and backward) operations with basic CMOS logic gates. The backward operation based on CMOS invertible logic makes hardware-based learning possible because the loss function is not required. For a simple case study, the proposed learning hardware trains using simplified a MNIST data set for a 25-input binarized perceptron. Our FPGA implementation on Digilent Genesys 2 achieves around 100 x faster operating speed than that using a traditional learning algorithm on software while maintaining the same recognition accuracy of 99%.

KW - Hamiltonian

KW - Spin gate

KW - Stochastic computing

UR - http://www.scopus.com/inward/record.url?scp=85079174186&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=85079174186&partnerID=8YFLogxK

U2 - 10.1109/ICECS46596.2019.8965097

DO - 10.1109/ICECS46596.2019.8965097

M3 - Conference contribution

AN - SCOPUS:85079174186

T3 - 2019 26th IEEE International Conference on Electronics, Circuits and Systems, ICECS 2019

SP - 115

EP - 116

BT - 2019 26th IEEE International Conference on Electronics, Circuits and Systems, ICECS 2019

PB - Institute of Electrical and Electronics Engineers Inc.

T2 - 26th IEEE International Conference on Electronics, Circuits and Systems, ICECS 2019

Y2 - 27 November 2019 through 29 November 2019

ER -