TY - GEN
T1 - FPGA implementation of binarized perceptron learning hardware using CMOS invertible logic
AU - Shin, Duckgyu
AU - Onizawa, Naoya
AU - Hanyu, Takahiro
N1 - Funding Information:
ACKNOWLEDGMENT This work was supported in part by JST PRESTO Grant Number JPMJPR18M5, MEXT Brainware LSI Project and the WISE Program for AI Electronics, Tohoku University.
Publisher Copyright:
© 2019 IEEE.
PY - 2019/11
Y1 - 2019/11
N2 - This paper introduces FPGA implementation of learning hardware for a neural network. The proposed learning hardware is designed using CMOS invertible logic that realizes probabilistic bidirectional (forward and backward) operations with basic CMOS logic gates. The backward operation based on CMOS invertible logic makes hardware-based learning possible because the loss function is not required. For a simple case study, the proposed learning hardware trains using simplified a MNIST data set for a 25-input binarized perceptron. Our FPGA implementation on Digilent Genesys 2 achieves around 100 x faster operating speed than that using a traditional learning algorithm on software while maintaining the same recognition accuracy of 99%.
AB - This paper introduces FPGA implementation of learning hardware for a neural network. The proposed learning hardware is designed using CMOS invertible logic that realizes probabilistic bidirectional (forward and backward) operations with basic CMOS logic gates. The backward operation based on CMOS invertible logic makes hardware-based learning possible because the loss function is not required. For a simple case study, the proposed learning hardware trains using simplified a MNIST data set for a 25-input binarized perceptron. Our FPGA implementation on Digilent Genesys 2 achieves around 100 x faster operating speed than that using a traditional learning algorithm on software while maintaining the same recognition accuracy of 99%.
KW - Hamiltonian
KW - Spin gate
KW - Stochastic computing
UR - http://www.scopus.com/inward/record.url?scp=85079174186&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=85079174186&partnerID=8YFLogxK
U2 - 10.1109/ICECS46596.2019.8965097
DO - 10.1109/ICECS46596.2019.8965097
M3 - Conference contribution
AN - SCOPUS:85079174186
T3 - 2019 26th IEEE International Conference on Electronics, Circuits and Systems, ICECS 2019
SP - 115
EP - 116
BT - 2019 26th IEEE International Conference on Electronics, Circuits and Systems, ICECS 2019
PB - Institute of Electrical and Electronics Engineers Inc.
T2 - 26th IEEE International Conference on Electronics, Circuits and Systems, ICECS 2019
Y2 - 27 November 2019 through 29 November 2019
ER -