FPGA implementation of a stereo matching processor based on window-parallel-and-pixel-parallel architecture

Masanori Hariyama; Naoto Yokoyama; Michitaka Kameyama; Yasuhiro Kobayashi

doi:10.1109/MWSCAS.2005.1594327

FPGA implementation of a stereo matching processor based on window-parallel-and-pixel-parallel architecture

Masanori Hariyama, Naoto Yokoyama, Michitaka Kameyama, Yasuhiro Kobayashi

INF - Computer and Mathematical Sciences

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

16 Citations (Scopus)

Abstract

This paper presents a processor architecture for high-speed and reliable stereo matching based on adaptive window-size control of SAD (Sum of Absolute Differences) computation. To reduce its computational complexity, SADs are computed using images divided into non-overlapping regions, and the matching result is iteratively refined by reducing a window size. Window-parallel-and- pixel-parallel architecture is also proposed to achieve to fully exploit the potential parallelism of the algorithm. The architecture also reduces the complexity of an interconnection network between memory and functional units based on the regularity of reference pixels. The stereo matching processor is implemented on an FPGA. Its performance is 80 times higher than that of a microprocessor(Pentium4@2GHz), and is enough to generate a 3-D depth image at the video rate of 33MHz.

Original language	English
Title of host publication	2005 IEEE International 48th Midwest Symposium on Circuits and Systems, MWSCAS 2005
Pages	1219-1222
Number of pages	4
DOIs	https://doi.org/10.1109/MWSCAS.2005.1594327
Publication status	Published - 2005 Dec 1
Event	2005 IEEE International 48th Midwest Symposium on Circuits and Systems, MWSCAS 2005 - Cincinnati, OH, United States Duration: 2005 Aug 7 → 2005 Aug 10

Publication series

Name	Midwest Symposium on Circuits and Systems
Volume	2005
ISSN (Print)	1548-3746

Other

Other	2005 IEEE International 48th Midwest Symposium on Circuits and Systems, MWSCAS 2005
Country/Territory	United States
City	Cincinnati, OH
Period	05/8/7 → 05/8/10

ASJC Scopus subject areas

Electronic, Optical and Magnetic Materials
Electrical and Electronic Engineering

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10.1109/MWSCAS.2005.1594327

Cite this

Hariyama, M., Yokoyama, N., Kameyama, M., & Kobayashi, Y. (2005). FPGA implementation of a stereo matching processor based on window-parallel-and-pixel-parallel architecture. In 2005 IEEE International 48th Midwest Symposium on Circuits and Systems, MWSCAS 2005 (pp. 1219-1222). [1594327] (Midwest Symposium on Circuits and Systems; Vol. 2005). https://doi.org/10.1109/MWSCAS.2005.1594327

FPGA implementation of a stereo matching processor based on window-parallel-and-pixel-parallel architecture. / Hariyama, Masanori; Yokoyama, Naoto; Kameyama, Michitaka et al.

2005 IEEE International 48th Midwest Symposium on Circuits and Systems, MWSCAS 2005. 2005. p. 1219-1222 1594327 (Midwest Symposium on Circuits and Systems; Vol. 2005).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Hariyama, M, Yokoyama, N, Kameyama, M & Kobayashi, Y 2005, FPGA implementation of a stereo matching processor based on window-parallel-and-pixel-parallel architecture. in 2005 IEEE International 48th Midwest Symposium on Circuits and Systems, MWSCAS 2005., 1594327, Midwest Symposium on Circuits and Systems, vol. 2005, pp. 1219-1222, 2005 IEEE International 48th Midwest Symposium on Circuits and Systems, MWSCAS 2005, Cincinnati, OH, United States, 05/8/7. https://doi.org/10.1109/MWSCAS.2005.1594327

@inproceedings{1a45ffbd070e466fb10f8a79b0e1d281,

title = "FPGA implementation of a stereo matching processor based on window-parallel-and-pixel-parallel architecture",

abstract = "This paper presents a processor architecture for high-speed and reliable stereo matching based on adaptive window-size control of SAD (Sum of Absolute Differences) computation. To reduce its computational complexity, SADs are computed using images divided into non-overlapping regions, and the matching result is iteratively refined by reducing a window size. Window-parallel-and- pixel-parallel architecture is also proposed to achieve to fully exploit the potential parallelism of the algorithm. The architecture also reduces the complexity of an interconnection network between memory and functional units based on the regularity of reference pixels. The stereo matching processor is implemented on an FPGA. Its performance is 80 times higher than that of a microprocessor(Pentium4@2GHz), and is enough to generate a 3-D depth image at the video rate of 33MHz.",

author = "Masanori Hariyama and Naoto Yokoyama and Michitaka Kameyama and Yasuhiro Kobayashi",

year = "2005",

month = dec,

day = "1",

doi = "10.1109/MWSCAS.2005.1594327",

language = "English",

isbn = "0780391977",

series = "Midwest Symposium on Circuits and Systems",

pages = "1219--1222",

booktitle = "2005 IEEE International 48th Midwest Symposium on Circuits and Systems, MWSCAS 2005",

note = "2005 IEEE International 48th Midwest Symposium on Circuits and Systems, MWSCAS 2005 ; Conference date: 07-08-2005 Through 10-08-2005",

}

TY - GEN

T1 - FPGA implementation of a stereo matching processor based on window-parallel-and-pixel-parallel architecture

AU - Hariyama, Masanori

AU - Yokoyama, Naoto

AU - Kameyama, Michitaka

AU - Kobayashi, Yasuhiro

PY - 2005/12/1

Y1 - 2005/12/1

N2 - This paper presents a processor architecture for high-speed and reliable stereo matching based on adaptive window-size control of SAD (Sum of Absolute Differences) computation. To reduce its computational complexity, SADs are computed using images divided into non-overlapping regions, and the matching result is iteratively refined by reducing a window size. Window-parallel-and- pixel-parallel architecture is also proposed to achieve to fully exploit the potential parallelism of the algorithm. The architecture also reduces the complexity of an interconnection network between memory and functional units based on the regularity of reference pixels. The stereo matching processor is implemented on an FPGA. Its performance is 80 times higher than that of a microprocessor(Pentium4@2GHz), and is enough to generate a 3-D depth image at the video rate of 33MHz.

AB - This paper presents a processor architecture for high-speed and reliable stereo matching based on adaptive window-size control of SAD (Sum of Absolute Differences) computation. To reduce its computational complexity, SADs are computed using images divided into non-overlapping regions, and the matching result is iteratively refined by reducing a window size. Window-parallel-and- pixel-parallel architecture is also proposed to achieve to fully exploit the potential parallelism of the algorithm. The architecture also reduces the complexity of an interconnection network between memory and functional units based on the regularity of reference pixels. The stereo matching processor is implemented on an FPGA. Its performance is 80 times higher than that of a microprocessor(Pentium4@2GHz), and is enough to generate a 3-D depth image at the video rate of 33MHz.

UR - http://www.scopus.com/inward/record.url?scp=33847169495&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=33847169495&partnerID=8YFLogxK

U2 - 10.1109/MWSCAS.2005.1594327

DO - 10.1109/MWSCAS.2005.1594327

M3 - Conference contribution

AN - SCOPUS:33847169495

SN - 0780391977

SN - 9780780391970

T3 - Midwest Symposium on Circuits and Systems

SP - 1219

EP - 1222

BT - 2005 IEEE International 48th Midwest Symposium on Circuits and Systems, MWSCAS 2005

T2 - 2005 IEEE International 48th Midwest Symposium on Circuits and Systems, MWSCAS 2005

Y2 - 7 August 2005 through 10 August 2005

ER -

FPGA implementation of a stereo matching processor based on window-parallel-and-pixel-parallel architecture

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