TY - GEN
T1 - FPGA implementation of a stereo matching processor based on window-parallel-and-pixel-parallel architecture
AU - Hariyama, Masanori
AU - Yokoyama, Naoto
AU - Kameyama, Michitaka
AU - Kobayashi, Yasuhiro
PY - 2005/12/1
Y1 - 2005/12/1
N2 - This paper presents a processor architecture for high-speed and reliable stereo matching based on adaptive window-size control of SAD (Sum of Absolute Differences) computation. To reduce its computational complexity, SADs are computed using images divided into non-overlapping regions, and the matching result is iteratively refined by reducing a window size. Window-parallel-and- pixel-parallel architecture is also proposed to achieve to fully exploit the potential parallelism of the algorithm. The architecture also reduces the complexity of an interconnection network between memory and functional units based on the regularity of reference pixels. The stereo matching processor is implemented on an FPGA. Its performance is 80 times higher than that of a microprocessor(Pentium4@2GHz), and is enough to generate a 3-D depth image at the video rate of 33MHz.
AB - This paper presents a processor architecture for high-speed and reliable stereo matching based on adaptive window-size control of SAD (Sum of Absolute Differences) computation. To reduce its computational complexity, SADs are computed using images divided into non-overlapping regions, and the matching result is iteratively refined by reducing a window size. Window-parallel-and- pixel-parallel architecture is also proposed to achieve to fully exploit the potential parallelism of the algorithm. The architecture also reduces the complexity of an interconnection network between memory and functional units based on the regularity of reference pixels. The stereo matching processor is implemented on an FPGA. Its performance is 80 times higher than that of a microprocessor(Pentium4@2GHz), and is enough to generate a 3-D depth image at the video rate of 33MHz.
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U2 - 10.1109/MWSCAS.2005.1594327
DO - 10.1109/MWSCAS.2005.1594327
M3 - Conference contribution
AN - SCOPUS:33847169495
SN - 0780391977
SN - 9780780391970
T3 - Midwest Symposium on Circuits and Systems
SP - 1219
EP - 1222
BT - 2005 IEEE International 48th Midwest Symposium on Circuits and Systems, MWSCAS 2005
T2 - 2005 IEEE International 48th Midwest Symposium on Circuits and Systems, MWSCAS 2005
Y2 - 7 August 2005 through 10 August 2005
ER -