FPGA-based systolic computational-memory array for scalable stencil computations

Kentaro Sano

Research output: Chapter in Book/Report/Conference proceedingChapter

7 Citations (Scopus)

Abstract

Stencil computation is one of the typical kernels of numerical simulations, which requires acceleration for high-performance computing (HPC). However, the low operational-intensity of stencil computation makes it difficult to fully exploit the peak performance of recent multi-core CPUs and accelerators such as GPUs. Building custom-computing machines using programmable-logic devices, such as FPGAs, has recently been considered as a way to efficiently accelerate numerical simulations. Given of the many logic elements and embedded coarse-grained modules, state-of-the-art FPGAs are nowadays expected to efficiently perform floating-point operations with sustained performance comparable to or higher than that given by CPUs and GPUs. This chapter describes a case study of an FPGA-based custom computing machine (CCM) for high-performance stencil computations: a systolic computational-memory array (SCM array) implemented on multiple FPGAs.

Original languageEnglish
Title of host publicationHigh-Performance Computing Using FPGAs
PublisherSpringer New York
Pages279-303
Number of pages25
Volume9781461417910
ISBN (Electronic)9781461417910
ISBN (Print)1461417902, 9781461417903
DOIs
Publication statusPublished - 2013 Mar 1

ASJC Scopus subject areas

  • Engineering(all)

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