The goal of this paper is to present the development status of the Field Programmable Gate Array (FPGA) based on-board computer for reconfigurable computing on space systems, which is currently under development at the Institute of Space Systems of the Universitaet Stuttgart. Together with the capability of reconfigurable computing, the extremely high throughputs and flexibilities of FPGAs due to their internal parallel processing mechanisms are the ideal solutions for future space applications. This computer is designed for Low Earth Orbit applications and especially optimized for small satellites. It is internally organized in a combination of multiple SRAM-FPGAs and Flash-FPGAs. In order to mitigate radiation effects, Single Event Upsets (SEUs) in the multi-chip redundant SRAM-FPGAs are monitored, detected, isolated and recovered from the monitoring Flash-FPGA, whose configuration memory is inherently immune against SEUs. The radiation effects on both these reconfigurable FPGAs and their mitigation methods are summarized. The developed breadboard model for the concept verification are illustrated. The first flight model of this computer designed for a small satellite will demonstrate reconfigurable computing for attitude control, image processing, and Ka-band high-speed communications.