Engineering
Field Programmable Gate Arrays
100%
Memory Array
66%
Reduction Mechanism
50%
Performance
25%
Demonstrates
25%
Computer Simulation
16%
Memory Bandwidth
16%
Finite Difference Method
16%
Benchmark
16%
Productivity
8%
Data Transfer
8%
Processing Element
8%
Performance Improvement
8%
Increasing Number
8%
Communication Channel
8%
Simulation Software
8%
Programmability
8%
Bandwidth Requirement
8%
Array Size
8%
Applications
8%
Simulation
8%
Design
8%
High Ratio
8%
Satisfies
8%
Lower End
8%
Computer Science
Memory Array
66%
Computation
50%
Reduction Mechanism
50%
Scalability
25%
Computing
25%
Benchmark
16%
Memory Bandwidth
16%
Power Efficient
16%
Communication
16%
Numerical Simulation
16%
Sustained Performance
8%
Input/Output
8%
Processing Element
8%
Kernel
8%
Memory Architecture
8%
Performance Improvement
8%
Peak Performance
8%
Data Access
8%
Computing Units
8%
Bandwidth Requirement
8%
Mesh Network
8%
Programmability
8%
Single Precision
8%
Partitioning Approach
8%
Simulation
8%
Application
8%
Design
8%
Earth and Planetary Sciences
Bandwidth
75%
Calculation
50%
Array
41%
Finite Difference Method
16%
Utilization
16%
Communication
16%
Delay
16%
Custom
16%
Feasibility
8%
Tradeoff
8%
Time Division Multiplexing
8%
Arithmetic
8%
Productivity
8%
Show
8%
Approach
8%
Simulation
8%
Boundary
8%
Running
8%
Flexibility
8%
Physics
Calculation
50%
Arrays
41%
Performance
25%
Utilization
16%
Communications
16%
Simulation
8%
Work
8%
Cycles
8%
Flexibility
8%
Running
8%
Chemistry
Communication
16%
Structure
8%
Energy
8%
Application
8%
Simulation
8%
Number
8%
Flexibility
8%