Formal design of multiple-valued arithmetic algorithms over galois fields and its application to cryptographic processor

Research output: Chapter in Book/Report/Conference proceedingConference contribution

6 Citations (Scopus)

Abstract

This paper presents a formal description of multiple-valued arithmetic algorithms over Galois Fields (GFs). Our graph-based method can be applied to any multiple-valued arithmetic circuit over GF(2 m). The proposed circuit description is formally verified by formula manipulation based on polynomial reduction using Groebner basis. In this paper, we first present the graph representation and its extension. We also present an application of the proposed method to cryptographic processor consisting of GF(2 m) arithmetic circuits. The target architecture considered here is a round-per-cycle loop architecture commonly used in the design of cryptographic processors. The proposed approach successfully describes the 128-bit data path and verifies it within 4 minutes.

Original languageEnglish
Title of host publicationProceedings - IEEE 42nd International Symposium on Multiple-Valued Logic, ISMVL 2012
Pages110-115
Number of pages6
DOIs
Publication statusPublished - 2012
Event42nd IEEE International Symposium on Multiple-Valued Logic, ISMVL 2012 - Victoria, BC, Canada
Duration: 2012 May 142012 May 16

Publication series

NameProceedings of The International Symposium on Multiple-Valued Logic
ISSN (Print)0195-623X

Other

Other42nd IEEE International Symposium on Multiple-Valued Logic, ISMVL 2012
CountryCanada
CityVictoria, BC
Period12/5/1412/5/16

Keywords

  • arithmetic algorithms
  • computer algebra
  • formal verification
  • multiple-valued logic

ASJC Scopus subject areas

  • Computer Science(all)
  • Mathematics(all)

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