Floating gate B4-flash memory technology utilizing novel programming scheme - Highly scalable, efficient and temperature independent programming

S. Shukuri, N. Ajika, M. Mihara, Y. Kawajiri, T. Ogura, K. Kobayashi, T. Endoh, M. Nakashima

Research output: Chapter in Book/Report/Conference proceedingConference contribution

3 Citations (Scopus)

Abstract

A floating gate B4-flash memory cell technology, which provides high speed programming with excellent programming efficiency for NOR architecture, has been developed. We have reported a pchannel SONOS type B4-flash cell utilizing novel Back Bias assisted Band-to-Band tunneling induced Hot-Electron(B4-HE) injection[1]. This paper demonstrates that B4-HE injection programming scheme can be easily evolved to a floating gate cell. By applying a moderate back bias to the cell during programming, the bit-line voltage can be reduced below the supply voltage, 1.8V. As a result, B4-flash can achieves high speed programming comparable to conventional NOR and high programming efficiency comparable to NAND flash at the same time. Basic operations of the floating gate B4-flash cells have been investigated. It is also confirmed that B4-HE injection programming provides very weak temperature dependency in comparison with CHE and FN injection, and does not have a negative impact to its reliability.

Original languageEnglish
Title of host publication2007 22nd IEEE Non-Volatile Semiconductor Memory Workshop, Proceedings, NVSMW
Pages30-31
Number of pages2
DOIs
Publication statusPublished - 2007 Dec 1
Event2007 22nd IEEE Non-Volatile Semiconductor Memory Workshop, NVSMW - Monterey, CA, United States
Duration: 2007 Aug 262007 Aug 30

Publication series

Name2007 22nd IEEE Non-Volatile Semiconductor Memory Workshop, Proceedings, NVSMW

Other

Other2007 22nd IEEE Non-Volatile Semiconductor Memory Workshop, NVSMW
CountryUnited States
CityMonterey, CA
Period07/8/2607/8/30

ASJC Scopus subject areas

  • Control and Systems Engineering
  • Electrical and Electronic Engineering

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