Abstract
A flexible processor based on the full-adder/D-flip-flop merged module (FDMM) has been proposed and fabricated. The developed FDMM has a unique ability to perform both logic and flip-flop functions with a small number of transistors by merging the common parts of both circuits, which will improve hardware efficiency. We have also developed a context memory block (CMB) to reconfigure the hardware dynamically. It enables us to write the next configuration in parallel into the flexible processor during processing, which reduces the overhead of actual reconfiguration time and improves the performance.
| Original language | English |
|---|---|
| Pages (from-to) | 2581-2584 |
| Number of pages | 4 |
| Journal | Japanese Journal of Applied Physics, Part 1: Regular Papers and Short Notes and Review Papers |
| Volume | 40 |
| Issue number | 4 B |
| DOIs | |
| Publication status | Published - 2001 Apr |
Keywords
- Dynamically reconfigurable hardware
- Multi-context architecture
- Reconfigurable logic array
- Software/hardware synthesis
ASJC Scopus subject areas
- Engineering(all)
- Physics and Astronomy(all)