Flexible processor based on full-adder/D-flip-flop merged module

S. Sakaidani, N. Miyamoto, T. Ohmi

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

Flexible processor based on full-adder/D-flip-flop merged module (FDMM) has been designed and fabricated. The developed FDMM has unique ability to perform both logic and flip-flop functions with a small transistor count by merging the common part of both circuits. We have also developed a context memory block to reconfigure the hardware dynamically. The flexible processor may fill a gap between hardware performance and software programmability to jump into novel computing such as software/hardware synthesis; "software accelerator".

Original languageEnglish
Title of host publicationProceedings of the ASP-DAC 2001
Subtitle of host publicationAsia and South Pacific Design Automation Conference 2001
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages35-36
Number of pages2
ISBN (Electronic)0780366336
DOIs
Publication statusPublished - 2001 Jan 1
EventAsia and South Pacific Design Automation Conference 2001, ASP-DAC 2001 - Yokohama, Japan
Duration: 2001 Jan 302001 Feb 2

Publication series

NameProceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC
Volume2001-January

Other

OtherAsia and South Pacific Design Automation Conference 2001, ASP-DAC 2001
CountryJapan
CityYokohama
Period01/1/3001/2/2

Keywords

  • Acceleration
  • CMOS technology
  • Design engineering
  • Field programmable gate arrays
  • Flip-flops
  • Hardware
  • Large scale integration
  • Logic circuits
  • Reconfigurable logic
  • Software performance

ASJC Scopus subject areas

  • Computer Science Applications
  • Computer Graphics and Computer-Aided Design
  • Electrical and Electronic Engineering

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  • Cite this

    Sakaidani, S., Miyamoto, N., & Ohmi, T. (2001). Flexible processor based on full-adder/D-flip-flop merged module. In Proceedings of the ASP-DAC 2001: Asia and South Pacific Design Automation Conference 2001 (pp. 35-36). [913276] (Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC; Vol. 2001-January). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/ASPDAC.2001.913276