Flexible processor based on full-adder/D-flip-flop merged module

S. Sakaidani; N. Miyamoto; T. Ohmi

doi:10.1109/ASPDAC.2001.913276

Flexible processor based on full-adder/D-flip-flop merged module

S. Sakaidani, N. Miyamoto, T. Ohmi

New Industry Creation Hatchery Center (NICHe)

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Abstract

Flexible processor based on full-adder/D-flip-flop merged module (FDMM) has been designed and fabricated. The developed FDMM has unique ability to perform both logic and flip-flop functions with a small transistor count by merging the common part of both circuits. We have also developed a context memory block to reconfigure the hardware dynamically. The flexible processor may fill a gap between hardware performance and software programmability to jump into novel computing such as software/hardware synthesis; "software accelerator".

Original language	English
Title of host publication	Proceedings of the ASP-DAC 2001
Subtitle of host publication	Asia and South Pacific Design Automation Conference 2001
Publisher	Institute of Electrical and Electronics Engineers Inc.
Pages	35-36
Number of pages	2
ISBN (Electronic)	0780366336
DOIs	https://doi.org/10.1109/ASPDAC.2001.913276
Publication status	Published - 2001 Jan 1
Event	Asia and South Pacific Design Automation Conference 2001, ASP-DAC 2001 - Yokohama, Japan Duration: 2001 Jan 30 → 2001 Feb 2

Publication series

Name	Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC
Volume	2001-January

Other

Other	Asia and South Pacific Design Automation Conference 2001, ASP-DAC 2001
Country/Territory	Japan
City	Yokohama
Period	01/1/30 → 01/2/2

Keywords

Acceleration
CMOS technology
Design engineering
Field programmable gate arrays
Flip-flops
Hardware
Large scale integration
Logic circuits
Reconfigurable logic
Software performance

ASJC Scopus subject areas

Computer Science Applications
Computer Graphics and Computer-Aided Design
Electrical and Electronic Engineering

Access to Document

10.1109/ASPDAC.2001.913276

Cite this

Sakaidani, S., Miyamoto, N., & Ohmi, T. (2001). Flexible processor based on full-adder/D-flip-flop merged module. In Proceedings of the ASP-DAC 2001: Asia and South Pacific Design Automation Conference 2001 (pp. 35-36). [913276] (Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC; Vol. 2001-January). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/ASPDAC.2001.913276

Flexible processor based on full-adder/D-flip-flop merged module. / Sakaidani, S.; Miyamoto, N.; Ohmi, T.

Proceedings of the ASP-DAC 2001: Asia and South Pacific Design Automation Conference 2001. Institute of Electrical and Electronics Engineers Inc., 2001. p. 35-36 913276 (Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC; Vol. 2001-January).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Sakaidani, S, Miyamoto, N & Ohmi, T 2001, Flexible processor based on full-adder/D-flip-flop merged module. in Proceedings of the ASP-DAC 2001: Asia and South Pacific Design Automation Conference 2001., 913276, Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC, vol. 2001-January, Institute of Electrical and Electronics Engineers Inc., pp. 35-36, Asia and South Pacific Design Automation Conference 2001, ASP-DAC 2001, Yokohama, Japan, 01/1/30. https://doi.org/10.1109/ASPDAC.2001.913276

Sakaidani S, Miyamoto N, Ohmi T. Flexible processor based on full-adder/D-flip-flop merged module. In Proceedings of the ASP-DAC 2001: Asia and South Pacific Design Automation Conference 2001. Institute of Electrical and Electronics Engineers Inc. 2001. p. 35-36. 913276. (Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC). https://doi.org/10.1109/ASPDAC.2001.913276

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Flexible processor based on full-adder/D-flip-flop merged module

Abstract

Publication series

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Keywords

ASJC Scopus subject areas

Access to Document

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