First demonstration of field-free SOT-MRAM with 0.35 ns write speed and 70 thermal stability under 400°C thermal tolerance by canted SOT structure and its advanced patterning/SOT channel technology

H. Honjo; T. V.A. Nguyen; S. Fukami; H. Sato; S. Ikeda; T. Hanyu; H. Ohno; T. Watanabe; T. Nasuno; C. Zhang; T. Tanigawa; S. Miura; H. Inoue; M. Niwa; T. Yoshiduka; Y. Noguchi; M. Yasuhira; A. Tamakoshi; M. Natsui; Y. Ma; H. Koike; Y. Takahashi; K. Furuya; H. Shen; T. Endoh

doi:10.1109/IEDM19573.2019.8993443

First demonstration of field-free SOT-MRAM with 0.35 ns write speed and 70 thermal stability under 400°C thermal tolerance by canted SOT structure and its advanced patterning/SOT channel technology

H. Honjo, T. V.A. Nguyen, S. Fukami, H. Sato, S. Ikeda, T. Hanyu, H. Ohno, T. Watanabe, T. Nasuno, C. Zhang, T. Tanigawa, S. Miura, H. Inoue, M. Niwa, T. Yoshiduka, Y. Noguchi, M. Yasuhira, A. Tamakoshi, M. Natsui, Y. MaH. Koike, Y. Takahashi, K. Furuya, H. Shen, T. Endoh

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

19 Citations (Scopus)

Abstract

For the first time, we demonstrated 55 nm-CMOS/ spin-orbit-torque-device hybrid magnetic random-access memory (SOT-MRAM) cell with magnetic field free writing. For field free writing, we developed canted SOT device under 300 mm BEOL process full compatible with 400°C thermal tolerance. Moreover, we developed its advanced process as follows; SOT channel layer PVD process for high spin Hall angle under 400°C thermal tolerance, low damage RIE technology of MTJ for high TMR/thermal stability factor (Δ) and ultra-smooth surface metal via process under SOT channel to reduce contact resistance.By above developed technologies, our canted SOT devices fabricated under a 400°C thermal tolerance successfully achieved fast write speed of 0.35 ns without an external magnetic field, a large enough Δ of 70 for non-volatile memory (retention time is over 10 years), and a high TMR ratio of 167%, for the first time. Moreover, we successfully demonstrated field free SOT-MRAM performance.

Original language	English
Title of host publication	2019 IEEE International Electron Devices Meeting, IEDM 2019
Publisher	Institute of Electrical and Electronics Engineers Inc.
ISBN (Electronic)	9781728140315
DOIs	https://doi.org/10.1109/IEDM19573.2019.8993443
Publication status	Published - 2019 Dec
Event	65th Annual IEEE International Electron Devices Meeting, IEDM 2019 - San Francisco, United States Duration: 2019 Dec 7 → 2019 Dec 11

Publication series

Name	Technical Digest - International Electron Devices Meeting, IEDM
Volume	2019-December
ISSN (Print)	0163-1918

Conference

Conference	65th Annual IEEE International Electron Devices Meeting, IEDM 2019
Country/Territory	United States
City	San Francisco
Period	19/12/7 → 19/12/11

ASJC Scopus subject areas

Electronic, Optical and Magnetic Materials
Condensed Matter Physics
Electrical and Electronic Engineering
Materials Chemistry

Access to Document

10.1109/IEDM19573.2019.8993443

Cite this

Honjo, H., Nguyen, T. V. A., Fukami, S., Sato, H., Ikeda, S., Hanyu, T., Ohno, H., Watanabe, T., Nasuno, T., Zhang, C., Tanigawa, T., Miura, S., Inoue, H., Niwa, M., Yoshiduka, T., Noguchi, Y., Yasuhira, M., Tamakoshi, A., Natsui, M., ... Endoh, T. (2019). First demonstration of field-free SOT-MRAM with 0.35 ns write speed and 70 thermal stability under 400°C thermal tolerance by canted SOT structure and its advanced patterning/SOT channel technology. In 2019 IEEE International Electron Devices Meeting, IEDM 2019 [8993443] (Technical Digest - International Electron Devices Meeting, IEDM; Vol. 2019-December). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/IEDM19573.2019.8993443

First demonstration of field-free SOT-MRAM with 0.35 ns write speed and 70 thermal stability under 400°C thermal tolerance by canted SOT structure and its advanced patterning/SOT channel technology. / Honjo, H.; Nguyen, T. V.A.; Fukami, S. et al.

2019 IEEE International Electron Devices Meeting, IEDM 2019. Institute of Electrical and Electronics Engineers Inc., 2019. 8993443 (Technical Digest - International Electron Devices Meeting, IEDM; Vol. 2019-December).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Honjo, H , Nguyen, TVA , Fukami, S, Sato, H, Ikeda, S , Hanyu, T , Ohno, H, Watanabe, T, Nasuno, T, Zhang, C, Tanigawa, T, Miura, S, Inoue, H, Niwa, M, Yoshiduka, T, Noguchi, Y, Yasuhira, M, Tamakoshi, A, Natsui, M , Ma, Y , Koike, H, Takahashi, Y, Furuya, K, Shen, H & Endoh, T 2019, First demonstration of field-free SOT-MRAM with 0.35 ns write speed and 70 thermal stability under 400°C thermal tolerance by canted SOT structure and its advanced patterning/SOT channel technology. in 2019 IEEE International Electron Devices Meeting, IEDM 2019., 8993443, Technical Digest - International Electron Devices Meeting, IEDM, vol. 2019-December, Institute of Electrical and Electronics Engineers Inc., 65th Annual IEEE International Electron Devices Meeting, IEDM 2019, San Francisco, United States, 19/12/7. https://doi.org/10.1109/IEDM19573.2019.8993443

Honjo H , Nguyen TVA , Fukami S, Sato H, Ikeda S , Hanyu T et al. First demonstration of field-free SOT-MRAM with 0.35 ns write speed and 70 thermal stability under 400°C thermal tolerance by canted SOT structure and its advanced patterning/SOT channel technology. In 2019 IEEE International Electron Devices Meeting, IEDM 2019. Institute of Electrical and Electronics Engineers Inc. 2019. 8993443. (Technical Digest - International Electron Devices Meeting, IEDM). https://doi.org/10.1109/IEDM19573.2019.8993443

Honjo, H. ; Nguyen, T. V.A. ; Fukami, S. et al. / First demonstration of field-free SOT-MRAM with 0.35 ns write speed and 70 thermal stability under 400°C thermal tolerance by canted SOT structure and its advanced patterning/SOT channel technology. 2019 IEEE International Electron Devices Meeting, IEDM 2019. Institute of Electrical and Electronics Engineers Inc., 2019. (Technical Digest - International Electron Devices Meeting, IEDM).

@inproceedings{abcb849cbaf449289ca5531a845a98cd,

title = "First demonstration of field-free SOT-MRAM with 0.35 ns write speed and 70 thermal stability under 400°C thermal tolerance by canted SOT structure and its advanced patterning/SOT channel technology",

abstract = "For the first time, we demonstrated 55 nm-CMOS/ spin-orbit-torque-device hybrid magnetic random-access memory (SOT-MRAM) cell with magnetic field free writing. For field free writing, we developed canted SOT device under 300 mm BEOL process full compatible with 400°C thermal tolerance. Moreover, we developed its advanced process as follows; SOT channel layer PVD process for high spin Hall angle under 400°C thermal tolerance, low damage RIE technology of MTJ for high TMR/thermal stability factor (Δ) and ultra-smooth surface metal via process under SOT channel to reduce contact resistance.By above developed technologies, our canted SOT devices fabricated under a 400°C thermal tolerance successfully achieved fast write speed of 0.35 ns without an external magnetic field, a large enough Δ of 70 for non-volatile memory (retention time is over 10 years), and a high TMR ratio of 167%, for the first time. Moreover, we successfully demonstrated field free SOT-MRAM performance.",

author = "H. Honjo and Nguyen, {T. V.A.} and S. Fukami and H. Sato and S. Ikeda and T. Hanyu and H. Ohno and T. Watanabe and T. Nasuno and C. Zhang and T. Tanigawa and S. Miura and H. Inoue and M. Niwa and T. Yoshiduka and Y. Noguchi and M. Yasuhira and A. Tamakoshi and M. Natsui and Y. Ma and H. Koike and Y. Takahashi and K. Furuya and H. Shen and T. Endoh",

note = "Funding Information: By applying advanced CMOS technology, our developed canted SOT-MRAM will open to high speed write non-volatile memory with x ns and sub-ns, as our developed canted SOT device already achieved 0.35 ns write speed. ACKNOWLEDGMENT This work was supported by ImPACT Program of CSTI, STT-MRAM R&D program under Industry-Academic collaboration of CIES consortium. REFERENCES [1] S. Ikeda et al., Nat. Mater. 9, 721 (2010). [2] H. Sato et al., Appl. Phys. Lett. 105, 062403 (2014). [3] H. Honjo et al., Symp. VLSI Tech. Dig., T160 (2015). [4] T. Endoh et al., J. Low Power Electron. Appl. 8, 44 (2018). [5] O. Golonzka et al., IEDM Tech. Dig. 18 1 1. (2018). [6] Y. J. Song et al., IEDM Tech. Dig. 18.2.1. (2018). [7] K. Lee et al., IEDM Tech. Dig. 27.1.1. (2018). [8] S. Fukami et al, VLSI Tech., T61 (2016). [9] K. Garello et al, VLSI Tech., T195 (2019). [10] C. Zhang et al., Appl. Phys. Lett., 109, 192405 (2016). [11] Y. Takeuchi et al. Appl. Phys. Lett. 112, 192408 (2018). [12] H. Sato et al., IEDM Tech. Dig.27.2.1. (2018). Publisher Copyright: {\textcopyright} 2019 IEEE.; 65th Annual IEEE International Electron Devices Meeting, IEDM 2019 ; Conference date: 07-12-2019 Through 11-12-2019",

year = "2019",

month = dec,

doi = "10.1109/IEDM19573.2019.8993443",

language = "English",

series = "Technical Digest - International Electron Devices Meeting, IEDM",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

booktitle = "2019 IEEE International Electron Devices Meeting, IEDM 2019",

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T1 - First demonstration of field-free SOT-MRAM with 0.35 ns write speed and 70 thermal stability under 400°C thermal tolerance by canted SOT structure and its advanced patterning/SOT channel technology

AU - Honjo, H.

AU - Nguyen, T. V.A.

AU - Fukami, S.

AU - Sato, H.

AU - Ikeda, S.

AU - Hanyu, T.

AU - Ohno, H.

AU - Watanabe, T.

AU - Nasuno, T.

AU - Zhang, C.

AU - Tanigawa, T.

AU - Miura, S.

AU - Inoue, H.

AU - Niwa, M.

AU - Yoshiduka, T.

AU - Noguchi, Y.

AU - Yasuhira, M.

AU - Tamakoshi, A.

AU - Natsui, M.

AU - Ma, Y.

AU - Koike, H.

AU - Takahashi, Y.

AU - Furuya, K.

AU - Shen, H.

AU - Endoh, T.

N1 - Funding Information: By applying advanced CMOS technology, our developed canted SOT-MRAM will open to high speed write non-volatile memory with x ns and sub-ns, as our developed canted SOT device already achieved 0.35 ns write speed. ACKNOWLEDGMENT This work was supported by ImPACT Program of CSTI, STT-MRAM R&D program under Industry-Academic collaboration of CIES consortium. REFERENCES [1] S. Ikeda et al., Nat. Mater. 9, 721 (2010). [2] H. Sato et al., Appl. Phys. Lett. 105, 062403 (2014). [3] H. Honjo et al., Symp. VLSI Tech. Dig., T160 (2015). [4] T. Endoh et al., J. Low Power Electron. Appl. 8, 44 (2018). [5] O. Golonzka et al., IEDM Tech. Dig. 18 1 1. (2018). [6] Y. J. Song et al., IEDM Tech. Dig. 18.2.1. (2018). [7] K. Lee et al., IEDM Tech. Dig. 27.1.1. (2018). [8] S. Fukami et al, VLSI Tech., T61 (2016). [9] K. Garello et al, VLSI Tech., T195 (2019). [10] C. Zhang et al., Appl. Phys. Lett., 109, 192405 (2016). [11] Y. Takeuchi et al. Appl. Phys. Lett. 112, 192408 (2018). [12] H. Sato et al., IEDM Tech. Dig.27.2.1. (2018). Publisher Copyright: © 2019 IEEE.

PY - 2019/12

Y1 - 2019/12

N2 - For the first time, we demonstrated 55 nm-CMOS/ spin-orbit-torque-device hybrid magnetic random-access memory (SOT-MRAM) cell with magnetic field free writing. For field free writing, we developed canted SOT device under 300 mm BEOL process full compatible with 400°C thermal tolerance. Moreover, we developed its advanced process as follows; SOT channel layer PVD process for high spin Hall angle under 400°C thermal tolerance, low damage RIE technology of MTJ for high TMR/thermal stability factor (Δ) and ultra-smooth surface metal via process under SOT channel to reduce contact resistance.By above developed technologies, our canted SOT devices fabricated under a 400°C thermal tolerance successfully achieved fast write speed of 0.35 ns without an external magnetic field, a large enough Δ of 70 for non-volatile memory (retention time is over 10 years), and a high TMR ratio of 167%, for the first time. Moreover, we successfully demonstrated field free SOT-MRAM performance.

AB - For the first time, we demonstrated 55 nm-CMOS/ spin-orbit-torque-device hybrid magnetic random-access memory (SOT-MRAM) cell with magnetic field free writing. For field free writing, we developed canted SOT device under 300 mm BEOL process full compatible with 400°C thermal tolerance. Moreover, we developed its advanced process as follows; SOT channel layer PVD process for high spin Hall angle under 400°C thermal tolerance, low damage RIE technology of MTJ for high TMR/thermal stability factor (Δ) and ultra-smooth surface metal via process under SOT channel to reduce contact resistance.By above developed technologies, our canted SOT devices fabricated under a 400°C thermal tolerance successfully achieved fast write speed of 0.35 ns without an external magnetic field, a large enough Δ of 70 for non-volatile memory (retention time is over 10 years), and a high TMR ratio of 167%, for the first time. Moreover, we successfully demonstrated field free SOT-MRAM performance.

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U2 - 10.1109/IEDM19573.2019.8993443

DO - 10.1109/IEDM19573.2019.8993443

M3 - Conference contribution

AN - SCOPUS:85081061506

T3 - Technical Digest - International Electron Devices Meeting, IEDM

BT - 2019 IEEE International Electron Devices Meeting, IEDM 2019

PB - Institute of Electrical and Electronics Engineers Inc.

T2 - 65th Annual IEEE International Electron Devices Meeting, IEDM 2019

Y2 - 7 December 2019 through 11 December 2019

ER -

First demonstration of field-free SOT-MRAM with 0.35 ns write speed and 70 thermal stability under 400°C thermal tolerance by canted SOT structure and its advanced patterning/SOT channel technology

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