Fine-grain multiple-valued reconfigurable VLSI using universal-literal- based cells

Nobuaki Okada, Michitaka Kameyama

Research output: Chapter in Book/Report/Conference proceedingConference contribution

3 Citations (Scopus)

Abstract

A fine-grain reconfigurable VLSI for various applications including arithmetic operations is developed. In the fine-grain architecture, it is important to define a cell function which leads to high utilization of a logic block and reduction of a switch block. From the point of view, a universal-literal-based multiple-valued cell suitable for bit-serial reconfigurable computation is proposed. One of an arbitrary 2-variable binary logic operation, an addition and a subtraction can be executed by one cell. Also, an nxn-bit multiplication can be executed by 4n cells. A series-gating differential-pair circuit is effectively employed for implementing a full-adder circuit of Sum and a universal literal circuit. Therefore, a very simple cell can be constructed using the circuit technology. Moreover, interconnection complexity can be reduced by utilizing multiple-valued signaling, where superposition of serial data bits and a start signal which indicates a head of one-word is introduced.

Original languageEnglish
Title of host publicationProceedings - 38th International Symposium on Multiple-Valued Logic, ISMVL 2008
Pages180-185
Number of pages6
DOIs
Publication statusPublished - 2008 Sep 3
Event38th International Symposium on Multiple-Valued Logic, ISMVL 2008 - Dallas, TX, United States
Duration: 2008 May 222008 May 24

Publication series

NameProceedings of The International Symposium on Multiple-Valued Logic
ISSN (Print)0195-623X

Other

Other38th International Symposium on Multiple-Valued Logic, ISMVL 2008
CountryUnited States
CityDallas, TX
Period08/5/2208/5/24

ASJC Scopus subject areas

  • Computer Science(all)
  • Mathematics(all)

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