Fine-grain multiple-valued reconfigurable VLSI using series-gating differential-pair circuits and its evaluation

Nobuaki Okada, Michitaka Kameyama

Research output: Contribution to journalArticlepeer-review

13 Citations (Scopus)

Abstract

A fine-grain reconfigurable VLSI for various appli cations ding arithmetic operations is developed. In the fine-grain arch itecture, it is important to define a cell function which leads to high utilization of a logic block and reduction of a switch block. From the point of view, a universal-literal-based multiple-valued cell suitable for bit-serial reconfigurable computation is proposed. A series-gating differential-pair circuit is effectively employed for implementing a full-adder circuit of Sum and a universal literal circuit. Therefore, a simple logic block can be constructed using the circuit technology. Moreover, interconnection complexity can be reduced by utilizing multiple-valued signaling, where superposition of serial data bits and a start signal which indicates heading of one-word is introduced. Differential-pair circuits are also effectively employed for current-output replication, which leads to high-speed signaling to adjacent cells The evaluation is done based on 90nm CMOS design rule, and it is made clear that the area of the proposed cell can be reduced to 78% in comparison with that of the CMOS implementatiuon. Moreover, its area-time product becomes 92% while the delay time is increased by 18%

Original languageEnglish
Pages (from-to)1437-1443
Number of pages7
JournalIEICE Transactions on Electronics
VolumeE91-C
Issue number9
DOIs
Publication statusPublished - 2008 Sep

Keywords

  • Direct allocation of CDFG
  • Fine-grain reconfigurable VLSI
  • Logic block
  • Multiple-valued source-coupled logic
  • Universal literal

ASJC Scopus subject areas

  • Electronic, Optical and Magnetic Materials
  • Electrical and Electronic Engineering

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