Fine-grain cell design for multiple-valued reconfigurable VLSI using a single differential-pair circuit

Haque Mohammad Munirul, Michitaka Kameyama

Research output: Chapter in Book/Report/Conference proceedingConference contribution

2 Citations (Scopus)

Abstract

This paper presents a fine-grain cell design for a Multiple-Valued (MV) reconfigurable VLSI using a single Differential-Pair Circuit (DPC). The VLSI involves a bitserial localized data transfer architecture. The cell consists of a Multiple-Valued Source-Coupled Logic (MVSCL)-based threshold logic gate, a dynamic latch and a switch block. The threshold logic gate consists of only one universal comparator. A single DPC is used as a component of the universal comparator. By using programmable current sources for the DPC, the driving capability of the cell and the weight of the output can be changed according to the reconfigured information. The DPC compares a multiple-valued (MV) input with a threshold which is provided by a programmable threshold voltage generator. This leads to the high utilization of the cell because almost all the universal comparators in the VLSI chip can be utilized effectively without idle states. Furthermore, fine-grain pipelining increases the throughput of the VLSI. The VLSI is designed using 0.18μm CMOS standard design rule. HSPICE simulation results show that, the throughput and the power consumption are greatly improved in comparison with the equivalent VLSI reported until now.

Original languageEnglish
Title of host publication36th International Symposium on Multiple-Valued Logic, 2006. ISMVL 2006
Number of pages1
DOIs
Publication statusPublished - 2006 Nov 21
Event36th International Symposium on Multiple-Valued Logic, 2006. ISMVL 2006 - Singapore, Singapore
Duration: 2006 May 172006 May 20

Publication series

NameProceedings of The International Symposium on Multiple-Valued Logic
ISSN (Print)0195-623X

Other

Other36th International Symposium on Multiple-Valued Logic, 2006. ISMVL 2006
CountrySingapore
CitySingapore
Period06/5/1706/5/20

ASJC Scopus subject areas

  • Computer Science(all)
  • Mathematics(all)

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    Munirul, H. M., & Kameyama, M. (2006). Fine-grain cell design for multiple-valued reconfigurable VLSI using a single differential-pair circuit. In 36th International Symposium on Multiple-Valued Logic, 2006. ISMVL 2006 [1623965] (Proceedings of The International Symposium on Multiple-Valued Logic). https://doi.org/10.1109/ISMVL.2006.22