Fin-height controlled PVD-TiN gate FinFET SRAM for enhancing noise margin

Y. X. Liu, Kazuhiko Endo, S. O'uchi, J. Tsukada, H. Yamauchi, Y. Ishikawa, K. Sakamoto, T. Matsukawa, M. Masahara, T. Kamei, T. Hayashida, A. Ogura

Research output: Chapter in Book/Report/Conference proceedingConference contribution

3 Citations (Scopus)

Abstract

PVD-TiN gate FinFET SRAM half-cells with different β-ratios and fin-height controlled transistors have successfully been fabricated using orientation-dependent wet etching and selective recess RIE. It was found that read static noise margin (SNM) increases significantly by controlling β from 1 to 2. With further increasing β, read SNM increases slightly. On the other hand, write margin shows weak dependence on β. By controlling the fin-heights of pass-gate (PG) and pull-up (PU) transistors to one-half pull-down (PD) transistors, i.e., β = 2, the read SNM was enhanced from 133 to 185 mV at VDD = 1 V. Scaled recess areas down to 103 nm square for low-fins have successfully been fabricated by optimized electron-beam lithography and RIE. The developed fin-height controlled technology is very useful for the fabrication of scaled SRAM without cell area increment.

Original languageEnglish
Title of host publication2010 Proceedings of the European Solid State Device Research Conference, ESSDERC 2010
Pages202-205
Number of pages4
DOIs
Publication statusPublished - 2010 Dec 15
Externally publishedYes
Event2010 European Solid State Device Research Conference, ESSDERC 2010 - Sevilla, Spain
Duration: 2010 Sep 142010 Sep 16

Publication series

Name2010 Proceedings of the European Solid State Device Research Conference, ESSDERC 2010

Other

Other2010 European Solid State Device Research Conference, ESSDERC 2010
CountrySpain
CitySevilla
Period10/9/1410/9/16

ASJC Scopus subject areas

  • Condensed Matter Physics

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