Ferroelectric-based functional pass-gate for fine-grain pipelined VLSI computation

Takahiro Hanyu, Hiromitsu Kimura, Michitaka Kameyama, Yoshikazu Fujimori, Takashi Nakamura, Hidemi Takasu

Research output: Contribution to journalConference articlepeer-review

9 Citations (Scopus)

Abstract

A functional pass-gate based on ferroelectrics for fine grain pipelined very large scale integration (VLSI) computation is discussed. A potential application of the VLSI computation is shown using a 250 MHz pipelined multiplier with 16 pipeline stages. The pipeline pitch is found by the delay of a single functional pass gate. The timing diagram in which the basic behavior of the proposed ferroelectric based serial adder is also demonstrated.

Original languageEnglish
Pages (from-to)208-209+460+195
JournalDigest of Technical Papers - IEEE International Solid-State Circuits Conference
Publication statusPublished - 2002
Event2002 IEEE International Solid-State Circuits Conference - San Francisco, CA, United States
Duration: 2002 Feb 32002 Feb 7

ASJC Scopus subject areas

  • Electronic, Optical and Magnetic Materials
  • Electrical and Electronic Engineering

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