TY - JOUR
T1 - Fermi-level pinning position modulation by Al-containing metal gate for cost-effective dual-metal/dual-high-k CMOS
AU - Kadoshima, M.
AU - Sugita, Y.
AU - Shiraishi, K.
AU - Watanabe, H.
AU - Ohta, A.
AU - Miyazaki, S.
AU - Nakajima, K.
AU - Chikyow, T.
AU - Yamada, K.
AU - Aminaka, T.
AU - Kurosawa, E.
AU - Matsuki, T.
AU - Aoyama, T.
AU - Nara, Y.
AU - Ohji, Y.
PY - 2007
Y1 - 2007
N2 - We propose here cost-effective gate-first dual-metal/dual-high-k CMOS technology in which Fermi-level pinning is "positively" utilized to reduce threshold voltages for the first time. After systematic investigation on the relation between oxygen vacancies in Hf-based high-k film and electrical characteristics, we concluded that the Fermi-level pinning is unavoidable in principle with a thin EOT, but is a stable phenomenon that should be intentionally utilized. In our proposed method, source of oxygen interstitials (Al) is contained in metal gate material for p-FET, and consequently the flamand voltage is properly modulated by "opposite" Fermi-level pinning due to the oxygen interstitials incorporated into the underlying high-k film after high temperature annealing. It is also noteworthy that this method is simple and cost-effective because the initial high-k films are identical for n- and p-FET but they are automatically converted into dual high-k after the annealing process.
AB - We propose here cost-effective gate-first dual-metal/dual-high-k CMOS technology in which Fermi-level pinning is "positively" utilized to reduce threshold voltages for the first time. After systematic investigation on the relation between oxygen vacancies in Hf-based high-k film and electrical characteristics, we concluded that the Fermi-level pinning is unavoidable in principle with a thin EOT, but is a stable phenomenon that should be intentionally utilized. In our proposed method, source of oxygen interstitials (Al) is contained in metal gate material for p-FET, and consequently the flamand voltage is properly modulated by "opposite" Fermi-level pinning due to the oxygen interstitials incorporated into the underlying high-k film after high temperature annealing. It is also noteworthy that this method is simple and cost-effective because the initial high-k films are identical for n- and p-FET but they are automatically converted into dual high-k after the annealing process.
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U2 - 10.1109/VLSIT.2007.4339729
DO - 10.1109/VLSIT.2007.4339729
M3 - Conference article
AN - SCOPUS:47249129868
SP - 66
EP - 67
JO - Digest of Technical Papers - Symposium on VLSI Technology
JF - Digest of Technical Papers - Symposium on VLSI Technology
SN - 0743-1562
M1 - 4339729
T2 - 2007 Symposium on VLSI Technology, VLSIT 2007
Y2 - 12 June 2007 through 14 June 2007
ER -