Fermi-level pinning position modulation by Al-containing metal gate for cost-effective dual-metal/dual-high-k CMOS

M. Kadoshima, Y. Sugita, K. Shiraishi, H. Watanabe, A. Ohta, S. Miyazaki, K. Nakajima, T. Chikyow, K. Yamada, T. Aminaka, E. Kurosawa, T. Matsuki, T. Aoyama, Y. Nara, Y. Ohji

Research output: Contribution to journalConference article

19 Citations (Scopus)

Abstract

We propose here cost-effective gate-first dual-metal/dual-high-k CMOS technology in which Fermi-level pinning is "positively" utilized to reduce threshold voltages for the first time. After systematic investigation on the relation between oxygen vacancies in Hf-based high-k film and electrical characteristics, we concluded that the Fermi-level pinning is unavoidable in principle with a thin EOT, but is a stable phenomenon that should be intentionally utilized. In our proposed method, source of oxygen interstitials (Al) is contained in metal gate material for p-FET, and consequently the flamand voltage is properly modulated by "opposite" Fermi-level pinning due to the oxygen interstitials incorporated into the underlying high-k film after high temperature annealing. It is also noteworthy that this method is simple and cost-effective because the initial high-k films are identical for n- and p-FET but they are automatically converted into dual high-k after the annealing process.

Original languageEnglish
Article number4339729
Pages (from-to)66-67
Number of pages2
JournalDigest of Technical Papers - Symposium on VLSI Technology
DOIs
Publication statusPublished - 2007 Dec 1
Externally publishedYes
Event2007 Symposium on VLSI Technology, VLSIT 2007 - Kyoto, Japan
Duration: 2007 Jun 122007 Jun 14

ASJC Scopus subject areas

  • Electrical and Electronic Engineering

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    Kadoshima, M., Sugita, Y., Shiraishi, K., Watanabe, H., Ohta, A., Miyazaki, S., Nakajima, K., Chikyow, T., Yamada, K., Aminaka, T., Kurosawa, E., Matsuki, T., Aoyama, T., Nara, Y., & Ohji, Y. (2007). Fermi-level pinning position modulation by Al-containing metal gate for cost-effective dual-metal/dual-high-k CMOS. Digest of Technical Papers - Symposium on VLSI Technology, 66-67. [4339729]. https://doi.org/10.1109/VLSIT.2007.4339729