Recent progress in FeRAM device and circuit technologies that are fully compatible with advanced logic CMOS is described. We have developed a ferroelectric capacitor of a CMVP (capacitor-on-Metal/Via-stacked-Plug) memory cell that is fabricated after the completion of multilevel metallization. A 0.35-μm 2T/2C FeRAM macro based on CMVP has been fabricated for smart card applications. The chip features a wide operation voltage range, high write/read endurance, low consumption current, and a flexible memory size. The CMVP technologies also enable a 0.25-μm ASIC SRAM macro to be nonvolatile (NV-SRAM: nonvolatile SRAM). The memory cell consists of a six-transistor SRAM cell and two stacked back-up ferroelectric capacitors. A Vdd/2 plate line architecture makes read/write fatigue virtually negligible.
|Number of pages||8|
|Journal||Proceedings of the Custom Integrated Circuits Conference|
|Publication status||Published - 2001 Jan 1|
|Event||IEEE 2001 Custom Integrated Circuits Conference - San Diego, CA, United States|
Duration: 2001 May 6 → 2001 May 9
ASJC Scopus subject areas
- Electrical and Electronic Engineering