And the resistivity of the Cu paste under the low temperature annealing condition. Through-Silicon-Via (TSV) formation is a key technology for the fabrication of 3-D IC with good performance. Cu TSV has been attracting attention because Cu has a low resistance that can significantly reduce RC delay. Currently, Cu TSV is formed by an electroplating method. But, it becomes increasingly difficult to fill Cu into small size holes with high aspect ratio. This is because a sputter seed layer has poor step coverage, which induces failure of Cu filling. On the other hand, large size holes of more than 20μm diameter requires a long process time to be filled by electroplating. The large size electroplated Cu also suffers from severe thermo-mechanical stress after post-annealing process. In addition, CMP process is necessary to remove Cu overburden on the top surface of TSV wafers. Recently, various new techniques have been proposed, which include paste printing [1-5], super critical fluid deposition , electroless seed deposition , and dipping . Among the proposed methods, the paste printing technique owns greatly foreseen advantages. However, production has not yet been feasible because of the existing bottlenecks; high resistivity (∼ 38μΩ.cm) of the Cu paste , serious formations of cracks and voids in the TSV filled with Ag nanoparticle pastes due to unavoidable shrinkage of sintered Ag particles and too long filling time (needed 4 cycles, with 14h for each) [3, 4]. A recent work reported the improvements on electrical resistivity and filling ability using a nano-sized low melting point alloy. However it was used for the vias of O25μm × 100μm in glass substrates .