## Abstract

Current computing systems are too slow for information processing because of the huge number of procedural steps required. A decrease in the number of calculation steps is essential for real-time information processing. We have developed two kinds of novel architectures for automatic elimination of redundant calculation steps. The first architecture employs the new digit-serial algorithm which eliminates redundant lower digit calculations according to the most-significant-digit-first (MSD-first) digit-serial calculation scheme. Basic components based on this architecture, which employ the redundant number system to limit carry propagation, have been developed. The MSD-first sequential vector quantization processor (VQP) is 3.7 times faster than ordinary digital systems as the result of eliminating redundant lower-bit calculation. The second architecture realizes a decrease in the number of complex calculation steps by excluding useless data before executing the complex calculations according to the characterized value of the data. About 90% of Manhattan-distance (MD) calculations in VQP are excluded by estimating the MD from the average distance.

Original language | English |
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Pages (from-to) | 1707-1714 |

Number of pages | 8 |

Journal | IEICE Transactions on Electronics |

Volume | E82-C |

Issue number | 9 |

Publication status | Published - 1999 Jan 1 |

## Keywords

- Digit-serial architecture
- MSD-first architecture
- Numerical characteristic
- Preprocessing architecture
- Vector quantization

## ASJC Scopus subject areas

- Electronic, Optical and Magnetic Materials
- Electrical and Electronic Engineering