A fast clock synchroniser that quickly adjusts the initial phase of the DPLL output clock to the input signal (receiver detector output) at the beginning of acquisition is proposed for burst QDPSK signal reception. The synchroniser performance is given in terms of nondetection rate (NDR) of the unique word following the clock synchronisation preamble. Measured results clearly indicate that the proposed synchoniser achieves faster synchronisation than the conventional binary quantised DPLL clock synchroniser.
- Circuit design
- Digital communication systems
ASJC Scopus subject areas
- Electrical and Electronic Engineering