Fast clock synchroniser using initial phase presetting DPLL (IPP-DPLL) for burst signal reception

K. Ohno, D. Adachi

Research output: Contribution to journalArticlepeer-review

4 Citations (Scopus)

Abstract

A fast clock synchroniser that quickly adjusts the initial phase of the DPLL output clock to the input signal (receiver detector output) at the beginning of acquisition is proposed for burst QDPSK signal reception. The synchroniser performance is given in terms of nondetection rate (NDR) of the unique word following the clock synchronisation preamble. Measured results clearly indicate that the proposed synchoniser achieves faster synchronisation than the conventional binary quantised DPLL clock synchroniser.

Original languageEnglish
Pages (from-to)1902-1904
Number of pages3
JournalElectronics Letters
Volume27
Issue number21
DOIs
Publication statusPublished - 1991 Sep 12
Externally publishedYes

Keywords

  • Circuit design
  • Digital communication systems

ASJC Scopus subject areas

  • Electrical and Electronic Engineering

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