TY - JOUR
T1 - Fair and consistent hardware evaluation of fourteen round two SHA-3 candidates
AU - Knežević, Miroslav
AU - Kobayashi, Kazuyuki
AU - Ikegami, Jun
AU - Matsuo, Shin'ichiro
AU - Satoh, Akashi
AU - Kocabas, Ünal
AU - Fan, Junfeng
AU - Katashita, Toshihiro
AU - Sugawara, Takeshi
AU - Sakiyama, Kazuo
AU - Verbauwhede, Ingrid
AU - Ohta, Kazuo
AU - Homma, Naofumi
AU - Aoki, Takafumi
N1 - Funding Information:
Manuscript received August 19, 2010; revised November 12, 2010 and January 24, 2011; accepted February 21, 2011. Date of publication April 29, 2011; date of current version April 06, 2012. This work was supported in part by the IAP Programme P6/26 BCRYPT of the Belgian State, by FWO Project G.0300.07, by the European Commission under Contract ICT-2007-216676 ECRYPT NoE phase II, by K.U.Leuven-BOF (OT/06/40), by the Research Council K.U.Leuven: GOA TENSE, by Strategic International Cooperative Program (Joint Research Type), Japan Science, and by Technology Agency.
PY - 2012/5
Y1 - 2012/5
N2 - The first contribution of our paper is that we propose a platform, a design strategy, and evaluation criteria for a fair and consistent hardware evaluation of the second-round SHA-3 candidates. Using a SASEBO-GII field-programmable gate array (FPGA) board as a common platform, combined with well defined hardware and software interfaces, we compare all 256-bit version candidates with respect to area, throughput, latency, power, and energy consumption. Our approach defines a standard testing harness for SHA-3 candidates, including the interface specification for the SHA-3 module on our testing platform. The second contribution is that we provide both FPGA and 90-nm CMOS application-specific integrated circuit (ASIC) synthesis results and thereby are able to compare the results. Our third contribution is that we release the source code of all the candidates and by using a common, fixed, publicly available platform, our claimed results become reproducible and open for a public verification.
AB - The first contribution of our paper is that we propose a platform, a design strategy, and evaluation criteria for a fair and consistent hardware evaluation of the second-round SHA-3 candidates. Using a SASEBO-GII field-programmable gate array (FPGA) board as a common platform, combined with well defined hardware and software interfaces, we compare all 256-bit version candidates with respect to area, throughput, latency, power, and energy consumption. Our approach defines a standard testing harness for SHA-3 candidates, including the interface specification for the SHA-3 module on our testing platform. The second contribution is that we provide both FPGA and 90-nm CMOS application-specific integrated circuit (ASIC) synthesis results and thereby are able to compare the results. Our third contribution is that we release the source code of all the candidates and by using a common, fixed, publicly available platform, our claimed results become reproducible and open for a public verification.
KW - Application-specific integrated circuit (ASIC)
KW - SASEBO-GII
KW - SHA-3 competition
KW - field-programmable gate array (FPGA)
KW - hardware evaluation
KW - hash function
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U2 - 10.1109/TVLSI.2011.2128353
DO - 10.1109/TVLSI.2011.2128353
M3 - Article
AN - SCOPUS:84859790347
VL - 20
SP - 827
EP - 840
JO - IEEE Transactions on Very Large Scale Integration (VLSI) Systems
JF - IEEE Transactions on Very Large Scale Integration (VLSI) Systems
SN - 1063-8210
IS - 5
M1 - 5756688
ER -
