Fabrication process design of dislocation-free semiconductor devices by using stress singularity parameters

H. Ohta, H. Miura, Y. Tamaki, T. Ikeda, C. Hashimoto, S. Ikeda

Research output: Contribution to journalArticlepeer-review

1 Citation (Scopus)

Abstract

During fabrication of semiconductor devices, the stresses on a silicon substrate sometimes cause dislocations and worsen the electric characteristics of the device. Therefore, a dislocation-free fabrication process needs to be developed to improve reliability. In this paper, a process design method using stress singularity parameters (K and λ) is proposed. In order to prevent the dislocation generation, the process parameters, such as the device structure, materials and process temperatures, are set to keep the stress singularity parameters (K and λ) under the critical values of dislocation generation Kdc. These parameters are predicted using FEM method considering the internal stress of thin films. The process design was applied to a bipolar transistor and a MOS transistor and the experimental results agreed very well with the prediction. It was confirmed that this new process design method is effective in improving device reliability.

Original languageEnglish
Pages (from-to)303-308
Number of pages6
JournalZairyo/Journal of the Society of Materials Science, Japan
Volume50
Issue number3
DOIs
Publication statusPublished - 2001 Mar
Externally publishedYes

Keywords

  • Dislocation
  • Silicon
  • Stress singularity parameters
  • Thin films

ASJC Scopus subject areas

  • Materials Science(all)
  • Condensed Matter Physics
  • Mechanics of Materials
  • Mechanical Engineering

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