A new bipolar process technology for sidewall base contact structure (SICOS) transistors and the effects of sidewall base contact width on device characteristics are described. The sidewall window width can be precisely controlled by utilizing the fabrication processes of the two-step oxidation of a sidewall surface (TOSS). Such a surface is made by using two-step etching of a silicon epitaxial layer and through the formation of two sidewall Si02and two sidewall Si3N4 layers. The key point in the TOSS processes is the optimization of the two sidewall Si3N4thicknesses. This is necessary to prevent the extension of the bird’s beak to the first sidewall Si02so that the sidewall w indow can be selectively opened and to prevent the generation of defects. This opening of the sidewall window is mainly controlled by the first etching depth of the silicon epitaxial layer. By applying the TOSS processes to a SICOS transistor, the sidewall window width can be controlled as desired. As a result, the dependences of breakdown voltage, junction capacitance, cutoff frequency, and switching speed on the sidewall window width are clarified.
ASJC Scopus subject areas
- Electronic, Optical and Magnetic Materials
- Electrical and Electronic Engineering