Fabrication of double-gate thin-film SOI MOSFETs using wafer bonding and polishing

H. Horie, S. Ando, T. Tanaka, M. Imai, Y. Arimoto, S. Hijiya

Research output: Contribution to conferencePaper

17 Citations (Scopus)

Abstract

Double-gate thin-film SOI MOSFETs have been developed for high-speed CMOS-ULSI. The important processes include planarization of the bonded surface by CVD SiO2 polishing, and low-temperature wafer bonding using BPSG film. The characteristics of the device are dramatically improved by using a double-gate structure with a 50 nm-thick Si layer. The drain current of a double-gate n-MOSFET is 3 times higher than that of a single-gate n-MOSFET. The maximum transconductance is 150 mS/mm, more than twice that of a single-gate n-MOSFET.

Original languageEnglish
Pages165-167
Number of pages3
DOIs
Publication statusPublished - 1991 Jan 1
Externally publishedYes
Event23rd International Conference on Solid State Devices and Materials - SSDM '91 - Yokohama, Jpn
Duration: 1991 Aug 271991 Aug 29

Other

Other23rd International Conference on Solid State Devices and Materials - SSDM '91
CityYokohama, Jpn
Period91/8/2791/8/29

ASJC Scopus subject areas

  • Engineering(all)

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    Horie, H., Ando, S., Tanaka, T., Imai, M., Arimoto, Y., & Hijiya, S. (1991). Fabrication of double-gate thin-film SOI MOSFETs using wafer bonding and polishing. 165-167. Paper presented at 23rd International Conference on Solid State Devices and Materials - SSDM '91, Yokohama, Jpn, . https://doi.org/10.7567/ssdm.1991.a-6-1