Fabrication of a SiGe-channel MOSFET containing high Ge fraction layer by low-pressure chemical vapor deposition

Kinya Goto; Junichi Murota; Takahiro Maeda; Reiner Schuetz; Kiyohito Aizawa; Roland Kircher; Kuniyoshi Yokoo; Shoichi Ono

Fabrication of a SiGe-channel MOSFET containing high Ge fraction layer by low-pressure chemical vapor deposition

Kinya Goto, Junichi Murota, Takahiro Maeda, Reiner Schuetz, Kiyohito Aizawa, Roland Kircher, Kuniyoshi Yokoo, Shoichi Ono

Research Institute of Electrical Communication (RIEC)

Research output: Contribution to conference › Paper › peer-review

5 Citations (Scopus)

Abstract

A method for growing the high quality strained epitaxial heterostructure as well as the fabrication of Si_1-xGe_x-channel pMOSFET containing a high Ge fraction layer have been investigated. It is found that lowering deposition temperature of the Si_1-xGe_x and Si capping layers is necessary with increasing Ge fraction in order to prevent an island growth of the heterostructure. Using optimized Si/Si_1-xGe_x/Si heterostructures with flat surfaces and interfaces, high performance Si_0.5Ge_0.5-channel pMOSFET has been achieved with the large mobility enhancement of about 70% at 300K and over 150% at 77K compared with those of MOSFET without Si_1-xGe_x-channel.

Original language	English
Pages	449-451
Number of pages	3
Publication status	Published - 1992 Dec 1
Event	Extended Abstracts of the 1992 International Conference on Solid State Devices and Materials - SSDM '92 - Tsukuba, Jpn Duration: 1992 Aug 26 → 1992 Aug 28

Other

Other	Extended Abstracts of the 1992 International Conference on Solid State Devices and Materials - SSDM '92
City	Tsukuba, Jpn
Period	92/8/26 → 92/8/28

ASJC Scopus subject areas

Engineering(all)

Cite this

Fabrication of a SiGe-channel MOSFET containing high Ge fraction layer by low-pressure chemical vapor deposition. / Goto, Kinya; Murota, Junichi; Maeda, Takahiro; Schuetz, Reiner; Aizawa, Kiyohito; Kircher, Roland; Yokoo, Kuniyoshi; Ono, Shoichi.

1992. 449-451 Paper presented at Extended Abstracts of the 1992 International Conference on Solid State Devices and Materials - SSDM '92, Tsukuba, Jpn.

Research output: Contribution to conference › Paper › peer-review

Goto, K, Murota, J, Maeda, T, Schuetz, R, Aizawa, K, Kircher, R, Yokoo, K & Ono, S 1992, 'Fabrication of a SiGe-channel MOSFET containing high Ge fraction layer by low-pressure chemical vapor deposition', Paper presented at Extended Abstracts of the 1992 International Conference on Solid State Devices and Materials - SSDM '92, Tsukuba, Jpn, 92/8/26 - 92/8/28 pp. 449-451.

Goto, Kinya ; Murota, Junichi ; Maeda, Takahiro ; Schuetz, Reiner ; Aizawa, Kiyohito ; Kircher, Roland ; Yokoo, Kuniyoshi ; Ono, Shoichi. / Fabrication of a SiGe-channel MOSFET containing high Ge fraction layer by low-pressure chemical vapor deposition. Paper presented at Extended Abstracts of the 1992 International Conference on Solid State Devices and Materials - SSDM '92, Tsukuba, Jpn.3 p.

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abstract = "A method for growing the high quality strained epitaxial heterostructure as well as the fabrication of Si1-xGex-channel pMOSFET containing a high Ge fraction layer have been investigated. It is found that lowering deposition temperature of the Si1-xGex and Si capping layers is necessary with increasing Ge fraction in order to prevent an island growth of the heterostructure. Using optimized Si/Si1-xGex/Si heterostructures with flat surfaces and interfaces, high performance Si0.5Ge0.5-channel pMOSFET has been achieved with the large mobility enhancement of about 70% at 300K and over 150% at 77K compared with those of MOSFET without Si1-xGex-channel.",

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AU - Goto, Kinya

AU - Murota, Junichi

AU - Maeda, Takahiro

AU - Schuetz, Reiner

AU - Aizawa, Kiyohito

AU - Kircher, Roland

AU - Yokoo, Kuniyoshi

AU - Ono, Shoichi

PY - 1992/12/1

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N2 - A method for growing the high quality strained epitaxial heterostructure as well as the fabrication of Si1-xGex-channel pMOSFET containing a high Ge fraction layer have been investigated. It is found that lowering deposition temperature of the Si1-xGex and Si capping layers is necessary with increasing Ge fraction in order to prevent an island growth of the heterostructure. Using optimized Si/Si1-xGex/Si heterostructures with flat surfaces and interfaces, high performance Si0.5Ge0.5-channel pMOSFET has been achieved with the large mobility enhancement of about 70% at 300K and over 150% at 77K compared with those of MOSFET without Si1-xGex-channel.

AB - A method for growing the high quality strained epitaxial heterostructure as well as the fabrication of Si1-xGex-channel pMOSFET containing a high Ge fraction layer have been investigated. It is found that lowering deposition temperature of the Si1-xGex and Si capping layers is necessary with increasing Ge fraction in order to prevent an island growth of the heterostructure. Using optimized Si/Si1-xGex/Si heterostructures with flat surfaces and interfaces, high performance Si0.5Ge0.5-channel pMOSFET has been achieved with the large mobility enhancement of about 70% at 300K and over 150% at 77K compared with those of MOSFET without Si1-xGex-channel.

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Fabrication of a SiGe-channel MOSFET containing high Ge fraction layer by low-pressure chemical vapor deposition

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