Fabrication of a magnetic-tunnel-junction-based nonvolatile logic-in-memory LSI with content-aware write error masking scheme achieving 92% storage capacity and 79% power reduction

Research output: Contribution to journalArticlepeer-review

6 Citations (Scopus)

Abstract

A magnetic-tunnel-junction (MTJ)-based video coding hardware with an MTJ-write-error-rate relaxation scheme as well as a nonvolatile storage capacity reduction technique is designed and fabricated in a 90 nm MOS and 75nm perpendicular MTJ process. The proposed MTJ-oriented dynamic error masking scheme suppresses the effect of write operation errors on the operation result of LSI, which results in the increase in an acceptable MTJ write error rate up to 7.8 times with less than 6% area overhead, while achieving 79% power reduction compared with that of the static-random-access-memory-based one.

Original languageEnglish
Article number04CN01
JournalJapanese journal of applied physics
Volume56
Issue number4
DOIs
Publication statusPublished - 2017 Apr

ASJC Scopus subject areas

  • Engineering(all)
  • Physics and Astronomy(all)

Fingerprint Dive into the research topics of 'Fabrication of a magnetic-tunnel-junction-based nonvolatile logic-in-memory LSI with content-aware write error masking scheme achieving 92% storage capacity and 79% power reduction'. Together they form a unique fingerprint.

Cite this