TY - JOUR
T1 - Fabrication of a magnetic tunnel junction-based 240-tile nonvolatile field-programmable gate array chip skipping wasted write operations for greedy power-reduced logic applications
AU - Suzuki, Daisuke
AU - Natsui, Masanori
AU - Mochizuki, Akira
AU - Miura, Sadahiko
AU - Honjo, Hiroaki
AU - Kinoshita, Keizo
AU - Sato, Hideo
AU - Ikeda, Shoji
AU - Endoh, Tetsuo
AU - Ohno, Hideo
AU - Hanyu, Takahiro
PY - 2013/11/21
Y1 - 2013/11/21
N2 - A nonvolatile field-programmable gate array (NVFPGA) test chip with 240 tiles (the basic components) in a 12 × 20 2D-array is fabricated by 90 nm CMOS and 70 nm magnetic tunnel junction (MTJ) technologies. Since not only circuit configuration data but also temporal data are still remained in the MTJ devices even when the power supply is cut off, standby power dissipation is completely eliminated by utilizing tile-level power gating. Power reduction is further accelerated by skipping wasted write operations of nonvolatile flip-flops (NVFFs) for storing temporal data when the temporal data and the stored one are the same. As a typical application, a motion-vector prediction function is implemented on the proposed NVFPGA, which results in a write power reduction of 77% compared to that of a conventional MTJ-based NVFPGA and a total power reduction of 70% compared to that of an SRAM-based FPGA.
AB - A nonvolatile field-programmable gate array (NVFPGA) test chip with 240 tiles (the basic components) in a 12 × 20 2D-array is fabricated by 90 nm CMOS and 70 nm magnetic tunnel junction (MTJ) technologies. Since not only circuit configuration data but also temporal data are still remained in the MTJ devices even when the power supply is cut off, standby power dissipation is completely eliminated by utilizing tile-level power gating. Power reduction is further accelerated by skipping wasted write operations of nonvolatile flip-flops (NVFFs) for storing temporal data when the temporal data and the stored one are the same. As a typical application, a motion-vector prediction function is implemented on the proposed NVFPGA, which results in a write power reduction of 77% compared to that of a conventional MTJ-based NVFPGA and a total power reduction of 70% compared to that of an SRAM-based FPGA.
KW - Field-programmable gate array
KW - Magnetic tunnel junction device
KW - Nonvolatile logic-in-memory architecture
KW - Power-gating
UR - http://www.scopus.com/inward/record.url?scp=84890352209&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=84890352209&partnerID=8YFLogxK
U2 - 10.1587/elex.10.20130772
DO - 10.1587/elex.10.20130772
M3 - Article
AN - SCOPUS:84890352209
VL - 10
JO - IEICE Electronics Express
JF - IEICE Electronics Express
SN - 1349-2543
IS - 23
M1 - 20130772
ER -