Fabrication of a 3000-6-input-LUTs embedded and block-level power-gated nonvolatile FPGA chip using p-MTJ-based logic-in-memory structure

D. Suzuki; M. Natsui; Akira Mochizuki; S. Miura; H. Honjo; H. Sato; S. Fukami; S. Ikeda; T. Endoh; H. Ohno; T. Hanyu

doi:10.1109/VLSIC.2015.7231371

Fabrication of a 3000-6-input-LUTs embedded and block-level power-gated nonvolatile FPGA chip using p-MTJ-based logic-in-memory structure

D. Suzuki, M. Natsui, Akira Mochizuki, S. Miura, H. Honjo, H. Sato, S. Fukami, S. Ikeda, T. Endoh, H. Ohno, T. Hanyu

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

14 Citations (Scopus)

Abstract

A nonvolatile FPGA (NVFPGA) test chip, where 3000 6-input lookup table (LUT) circuits are embedded, is fabricated under 90nm CMOS/75nm perpendicular magnetic tunnel junction (p-MTJ) technologies. The use of a p-MTJ device makes data-backup-limitation free, which essentially eliminates damage control to nonvolatile storage devices. The use of a p-MTJ device also enables the extension towards dynamically reconfigurable logic paradigm. Since hardware components are shared among all the p-MTJ devices by the use of logic-in-memory structure, the effective area of the 6-input LUT circuit is reduced by 56% compared to that of an SRAM-based one. Moreover, block-level power gating, in which all the idle function blocks are optimally turned off in accordance with the operation mode, can minimize static power consumption of each tile. As a result, the total average power of the proposed NVFPGA is reduced by 81% in comparison with that of an SRAM-based FPGA under typical benchmark-circuit realizations.

Original language	English
Title of host publication	2015 Symposium on VLSI Circuits, VLSI Circuits 2015
Publisher	Institute of Electrical and Electronics Engineers Inc.
Pages	C172-C173
ISBN (Electronic)	9784863485020
DOIs	https://doi.org/10.1109/VLSIC.2015.7231371
Publication status	Published - 2015 Aug 31
Event	29th Annual Symposium on VLSI Circuits, VLSI Circuits 2015 - Kyoto, Japan Duration: 2015 Jun 17 → 2015 Jun 19

Publication series

Name	IEEE Symposium on VLSI Circuits, Digest of Technical Papers
Volume	2015-August

Other

Other	29th Annual Symposium on VLSI Circuits, VLSI Circuits 2015
Country	Japan
City	Kyoto
Period	15/6/17 → 15/6/19

ASJC Scopus subject areas

Electronic, Optical and Magnetic Materials
Electrical and Electronic Engineering

Access to Document

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Suzuki, D., Natsui, M., Mochizuki, A., Miura, S., Honjo, H., Sato, H., Fukami, S., Ikeda, S., Endoh, T., Ohno, H., & Hanyu, T. (2015). Fabrication of a 3000-6-input-LUTs embedded and block-level power-gated nonvolatile FPGA chip using p-MTJ-based logic-in-memory structure. In 2015 Symposium on VLSI Circuits, VLSI Circuits 2015 (pp. C172-C173). [7231371] (IEEE Symposium on VLSI Circuits, Digest of Technical Papers; Vol. 2015-August). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/VLSIC.2015.7231371

Fabrication of a 3000-6-input-LUTs embedded and block-level power-gated nonvolatile FPGA chip using p-MTJ-based logic-in-memory structure. / Suzuki, D.; Natsui, M.; Mochizuki, Akira; Miura, S.; Honjo, H.; Sato, H.; Fukami, S.; Ikeda, S.; Endoh, T.; Ohno, H.; Hanyu, T.

2015 Symposium on VLSI Circuits, VLSI Circuits 2015. Institute of Electrical and Electronics Engineers Inc., 2015. p. C172-C173 7231371 (IEEE Symposium on VLSI Circuits, Digest of Technical Papers; Vol. 2015-August).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Suzuki, D, Natsui, M, Mochizuki, A, Miura, S , Honjo, H, Sato, H, Fukami, S , Ikeda, S , Endoh, T , Ohno, H & Hanyu, T 2015, Fabrication of a 3000-6-input-LUTs embedded and block-level power-gated nonvolatile FPGA chip using p-MTJ-based logic-in-memory structure. in 2015 Symposium on VLSI Circuits, VLSI Circuits 2015., 7231371, IEEE Symposium on VLSI Circuits, Digest of Technical Papers, vol. 2015-August, Institute of Electrical and Electronics Engineers Inc., pp. C172-C173, 29th Annual Symposium on VLSI Circuits, VLSI Circuits 2015, Kyoto, Japan, 15/6/17. https://doi.org/10.1109/VLSIC.2015.7231371

Suzuki D, Natsui M, Mochizuki A, Miura S , Honjo H, Sato H et al. Fabrication of a 3000-6-input-LUTs embedded and block-level power-gated nonvolatile FPGA chip using p-MTJ-based logic-in-memory structure. In 2015 Symposium on VLSI Circuits, VLSI Circuits 2015. Institute of Electrical and Electronics Engineers Inc. 2015. p. C172-C173. 7231371. (IEEE Symposium on VLSI Circuits, Digest of Technical Papers). https://doi.org/10.1109/VLSIC.2015.7231371

Suzuki, D. ; Natsui, M. ; Mochizuki, Akira ; Miura, S. ; Honjo, H. ; Sato, H. ; Fukami, S. ; Ikeda, S. ; Endoh, T. ; Ohno, H. ; Hanyu, T. / Fabrication of a 3000-6-input-LUTs embedded and block-level power-gated nonvolatile FPGA chip using p-MTJ-based logic-in-memory structure. 2015 Symposium on VLSI Circuits, VLSI Circuits 2015. Institute of Electrical and Electronics Engineers Inc., 2015. pp. C172-C173 (IEEE Symposium on VLSI Circuits, Digest of Technical Papers).

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abstract = "A nonvolatile FPGA (NVFPGA) test chip, where 3000 6-input lookup table (LUT) circuits are embedded, is fabricated under 90nm CMOS/75nm perpendicular magnetic tunnel junction (p-MTJ) technologies. The use of a p-MTJ device makes data-backup-limitation free, which essentially eliminates damage control to nonvolatile storage devices. The use of a p-MTJ device also enables the extension towards dynamically reconfigurable logic paradigm. Since hardware components are shared among all the p-MTJ devices by the use of logic-in-memory structure, the effective area of the 6-input LUT circuit is reduced by 56% compared to that of an SRAM-based one. Moreover, block-level power gating, in which all the idle function blocks are optimally turned off in accordance with the operation mode, can minimize static power consumption of each tile. As a result, the total average power of the proposed NVFPGA is reduced by 81% in comparison with that of an SRAM-based FPGA under typical benchmark-circuit realizations.",

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