TY - GEN
T1 - Fabrication of a 3000-6-input-LUTs embedded and block-level power-gated nonvolatile FPGA chip using p-MTJ-based logic-in-memory structure
AU - Suzuki, D.
AU - Natsui, M.
AU - Mochizuki, Akira
AU - Miura, S.
AU - Honjo, H.
AU - Sato, H.
AU - Fukami, S.
AU - Ikeda, S.
AU - Endoh, T.
AU - Ohno, H.
AU - Hanyu, T.
PY - 2015/8/31
Y1 - 2015/8/31
N2 - A nonvolatile FPGA (NVFPGA) test chip, where 3000 6-input lookup table (LUT) circuits are embedded, is fabricated under 90nm CMOS/75nm perpendicular magnetic tunnel junction (p-MTJ) technologies. The use of a p-MTJ device makes data-backup-limitation free, which essentially eliminates damage control to nonvolatile storage devices. The use of a p-MTJ device also enables the extension towards dynamically reconfigurable logic paradigm. Since hardware components are shared among all the p-MTJ devices by the use of logic-in-memory structure, the effective area of the 6-input LUT circuit is reduced by 56% compared to that of an SRAM-based one. Moreover, block-level power gating, in which all the idle function blocks are optimally turned off in accordance with the operation mode, can minimize static power consumption of each tile. As a result, the total average power of the proposed NVFPGA is reduced by 81% in comparison with that of an SRAM-based FPGA under typical benchmark-circuit realizations.
AB - A nonvolatile FPGA (NVFPGA) test chip, where 3000 6-input lookup table (LUT) circuits are embedded, is fabricated under 90nm CMOS/75nm perpendicular magnetic tunnel junction (p-MTJ) technologies. The use of a p-MTJ device makes data-backup-limitation free, which essentially eliminates damage control to nonvolatile storage devices. The use of a p-MTJ device also enables the extension towards dynamically reconfigurable logic paradigm. Since hardware components are shared among all the p-MTJ devices by the use of logic-in-memory structure, the effective area of the 6-input LUT circuit is reduced by 56% compared to that of an SRAM-based one. Moreover, block-level power gating, in which all the idle function blocks are optimally turned off in accordance with the operation mode, can minimize static power consumption of each tile. As a result, the total average power of the proposed NVFPGA is reduced by 81% in comparison with that of an SRAM-based FPGA under typical benchmark-circuit realizations.
UR - http://www.scopus.com/inward/record.url?scp=84957867185&partnerID=8YFLogxK
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U2 - 10.1109/VLSIC.2015.7231371
DO - 10.1109/VLSIC.2015.7231371
M3 - Conference contribution
AN - SCOPUS:84957867185
T3 - IEEE Symposium on VLSI Circuits, Digest of Technical Papers
SP - C172-C173
BT - 2015 Symposium on VLSI Circuits, VLSI Circuits 2015
PB - Institute of Electrical and Electronics Engineers Inc.
T2 - 29th Annual Symposium on VLSI Circuits, VLSI Circuits 2015
Y2 - 17 June 2015 through 19 June 2015
ER -