Fabrication of a 3000-6-input-LUTs embedded and block-level power-gated nonvolatile FPGA chip using p-MTJ-based logic-in-memory structure

Daisuke Suzuki, M. Natsui, Akira Mochizuki, S. Miura, H. Honjo, Hideo Sato, S. Fukami, S. Ikeda, T. Endoh, H. Ohno, T. Hanyu

Research output: Chapter in Book/Report/Conference proceedingConference contribution

23 Citations (Scopus)

Abstract

A nonvolatile FPGA (NVFPGA) test chip, where 3000 6-input lookup table (LUT) circuits are embedded, is fabricated under 90nm CMOS/75nm perpendicular magnetic tunnel junction (p-MTJ) technologies. The use of a p-MTJ device makes data-backup-limitation free, which essentially eliminates damage control to nonvolatile storage devices. The use of a p-MTJ device also enables the extension towards dynamically reconfigurable logic paradigm. Since hardware components are shared among all the p-MTJ devices by the use of logic-in-memory structure, the effective area of the 6-input LUT circuit is reduced by 56% compared to that of an SRAM-based one. Moreover, block-level power gating, in which all the idle function blocks are optimally turned off in accordance with the operation mode, can minimize static power consumption of each tile. As a result, the total average power of the proposed NVFPGA is reduced by 81% in comparison with that of an SRAM-based FPGA under typical benchmark-circuit realizations.

Original languageEnglish
Title of host publication2015 Symposium on VLSI Technology, VLSI Technology 2015 - Digest of Technical Papers
PublisherInstitute of Electrical and Electronics Engineers Inc.
PagesC172-C173
ISBN (Electronic)9784863485013
DOIs
Publication statusPublished - 2015 Aug 25
EventSymposium on VLSI Technology, VLSI Technology 2015 - Kyoto, Japan
Duration: 2015 Jun 162015 Jun 18

Publication series

NameDigest of Technical Papers - Symposium on VLSI Technology
Volume2015-August
ISSN (Print)0743-1562

Other

OtherSymposium on VLSI Technology, VLSI Technology 2015
CountryJapan
CityKyoto
Period15/6/1615/6/18

ASJC Scopus subject areas

  • Electrical and Electronic Engineering

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    Suzuki, D., Natsui, M., Mochizuki, A., Miura, S., Honjo, H., Sato, H., Fukami, S., Ikeda, S., Endoh, T., Ohno, H., & Hanyu, T. (2015). Fabrication of a 3000-6-input-LUTs embedded and block-level power-gated nonvolatile FPGA chip using p-MTJ-based logic-in-memory structure. In 2015 Symposium on VLSI Technology, VLSI Technology 2015 - Digest of Technical Papers (pp. C172-C173). [7223644] (Digest of Technical Papers - Symposium on VLSI Technology; Vol. 2015-August). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/VLSIT.2015.7223644