Fabrication and characterization of vertical-type double-gate metal-oxide-semiconductor field-effect transistor with ultrathin Si channel and self-aligned source and drain

Meishoku Masahara, Yongxun Liu, Kazuhiko Endo, Takashi Matsukawa, Kunihiro Sakamoto, Kenichi Ishii, Shinichi O'uchi, Etsuro Sugimata, Hiromi Yamauchi, Eiichi Suzuki

Research output: Contribution to journalArticlepeer-review

8 Citations (Scopus)

Abstract

A fabrication technique for a vertical double-gate metal-oxide- semiconductor field-effect transistor (DG MOSFET) with a standing-up ultrathin channel (UTC) and self-aligned source and drain (S/D) is proposed. A 20 nm thick vertical UTC with low channel thickness fluctuation was formed on a (110)-oriented Si substrate using orientation-dependent wet etching. The top and bottom S/D were self-aligned to the DGs by using a combination of ion implantation and solid-phase diffusion. The fabricated vertical DG MOSFETs revealed that the channel thickness less influences the threshold voltage. Furthermore, a low sub-threshold slope of 68.8 mV /decade was achieved with a channel thickness of 20 nm.

Original languageEnglish
Article number072103
JournalApplied Physics Letters
Volume88
Issue number7
DOIs
Publication statusPublished - 2006 Feb 24
Externally publishedYes

ASJC Scopus subject areas

  • Physics and Astronomy (miscellaneous)

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