Abstract
A fabrication technique for a vertical double-gate metal-oxide- semiconductor field-effect transistor (DG MOSFET) with a standing-up ultrathin channel (UTC) and self-aligned source and drain (S/D) is proposed. A 20 nm thick vertical UTC with low channel thickness fluctuation was formed on a (110)-oriented Si substrate using orientation-dependent wet etching. The top and bottom S/D were self-aligned to the DGs by using a combination of ion implantation and solid-phase diffusion. The fabricated vertical DG MOSFETs revealed that the channel thickness less influences the threshold voltage. Furthermore, a low sub-threshold slope of 68.8 mV /decade was achieved with a channel thickness of 20 nm.
Original language | English |
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Article number | 072103 |
Journal | Applied Physics Letters |
Volume | 88 |
Issue number | 7 |
DOIs | |
Publication status | Published - 2006 Feb 24 |
Externally published | Yes |
ASJC Scopus subject areas
- Physics and Astronomy (miscellaneous)