Abstract
Although 3D integration technologies with through silicon vias (TSVs) have expected to overcome the memory and power wall problems in the future microprocessor design, there is no promising EDA tools to design 3D integrated VLSIs. In addition, effects of 3D integration on microprocessor design have not been discussed well. Under this situation, this paper presents design approach of 3D stacked cache memories using existing EDA tools, and shows early performances evaluation of 3D stacked cache memories for vector processors.
| Original language | English |
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| Title of host publication | Proceedings - 2012 SC Companion |
| Subtitle of host publication | High Performance Computing, Networking Storage and Analysis, SCC 2012 |
| Pages | 1475-1477 |
| Number of pages | 3 |
| DOIs | |
| Publication status | Published - 2012 Dec 1 |
| Event | 2012 SC Companion: High Performance Computing, Networking Storage and Analysis, SCC 2012 - Salt Lake City, UT, United States Duration: 2012 Nov 10 → 2012 Nov 16 |
Publication series
| Name | Proceedings - 2012 SC Companion: High Performance Computing, Networking Storage and Analysis, SCC 2012 |
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Other
| Other | 2012 SC Companion: High Performance Computing, Networking Storage and Analysis, SCC 2012 |
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| Country | United States |
| City | Salt Lake City, UT |
| Period | 12/11/10 → 12/11/16 |
ASJC Scopus subject areas
- Computational Theory and Mathematics
- Computer Science Applications
- Software
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Cite this
Egawa, R., Tada, J., Endo, Y., Takizawa, H., & Kobayashi, H. (2012). Exploring design space of a 3D stacked vector cache. In Proceedings - 2012 SC Companion: High Performance Computing, Networking Storage and Analysis, SCC 2012 (pp. 1475-1477). [6496053] (Proceedings - 2012 SC Companion: High Performance Computing, Networking Storage and Analysis, SCC 2012). https://doi.org/10.1109/SC.Companion.2012.270