TY - GEN
T1 - Exploring design space of a 3D stacked vector cache
AU - Egawa, Ryusuke
AU - Tada, Jubee
AU - Endo, Yusuke
AU - Takizawa, Hiroyuki
AU - Kobayashi, Hiroaki
PY - 2012
Y1 - 2012
N2 - Although 3D integration technologies with through silicon vias (TSVs) have expected to overcome the memory and power wall problems in the future microprocessor design, there is no promising EDA tools to design 3D integrated VLSIs. In addition, effects of 3D integration on microprocessor design have not been discussed well. Under this situation, this paper presents design approach of 3D stacked cache memories using existing EDA tools, and shows early performances evaluation of 3D stacked cache memories for vector processors.
AB - Although 3D integration technologies with through silicon vias (TSVs) have expected to overcome the memory and power wall problems in the future microprocessor design, there is no promising EDA tools to design 3D integrated VLSIs. In addition, effects of 3D integration on microprocessor design have not been discussed well. Under this situation, this paper presents design approach of 3D stacked cache memories using existing EDA tools, and shows early performances evaluation of 3D stacked cache memories for vector processors.
UR - http://www.scopus.com/inward/record.url?scp=84876589248&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=84876589248&partnerID=8YFLogxK
U2 - 10.1109/SC.Companion.2012.270
DO - 10.1109/SC.Companion.2012.270
M3 - Conference contribution
AN - SCOPUS:84876589248
SN - 9780769549569
T3 - Proceedings - 2012 SC Companion: High Performance Computing, Networking Storage and Analysis, SCC 2012
SP - 1475
EP - 1477
BT - Proceedings - 2012 SC Companion
T2 - 2012 SC Companion: High Performance Computing, Networking Storage and Analysis, SCC 2012
Y2 - 10 November 2012 through 16 November 2012
ER -