Exploring a design space of 3-D stacked vector processors

Ryusuke Egawa, Jubee Tada, Hiroaki Kobayashi

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

Three dimensional (3-D) technologies have come under the spotlight to overcome limitations of conventional two dimensional (2-D) microprocessor implementations. However, the effect of 3-D integrations with vertical interconnects in future vector processors design is not well discussed yet. In this paper, aiming at exploring the design space of future vector processors, fine and coarse grain 3-D integrations that aggressively employ vertical interconnects are designed and evaluated.

Original languageEnglish
Title of host publicationSustained Simulation Performance 2012 - Proceedings of the Joint Workshop on High Performance Computing on Vector Systems, and Workshop on Sustained Simulation Performance
PublisherSpringer Science and Business Media, LLC
Pages35-49
Number of pages15
ISBN (Print)9783642324536
DOIs
Publication statusPublished - 2013
EventJoint Workshop on High Performance Computing on Vector Systems and 15th Workshop on Sustained Simulation Performance 2012 - Sendai, Japan
Duration: 2012 Mar 12012 Mar 1

Publication series

NameSustained Simulation Performance 2012 - Proceedings of the Joint Workshop on High Performance Computing on Vector Systems, and Workshop on Sustained Simulation Performance

Other

OtherJoint Workshop on High Performance Computing on Vector Systems and 15th Workshop on Sustained Simulation Performance 2012
CountryJapan
CitySendai
Period12/3/112/3/1

ASJC Scopus subject areas

  • Modelling and Simulation

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