Experimental study of tri-gate SOI-FinFET flash memory

Y. X. Liu, T. Kamei, T. Matsukawa, K. Endo, S. O'Uchi, J. Tsukada, H. Yamauchi, Y. Ishikawa, T. Hayashida, K. Sakamoto, A. Ogura, M. Masahara

Research output: Chapter in Book/Report/Conference proceedingConference contribution

1 Citation (Scopus)

Abstract

It is well known that 3D channel devices, such as double-gate (DG) and tri-gate (TG) FinFETs, provide excellent short-channel effect (SCE) immunity. Thus, the scaled 3D channel FinFET flash memories with oxide-nitride-oxide (ONO) charge trapping layers have actively been developed [1-3]. Very recently, we have also developed floating-gate (FG) type SOI-FinFET flash memories [4-7]. In this paper, we report the experimental results of the FG type SOI-FinFET flash memories including gate structure dependent of Vt variability and SCE immunity. We also report the FinFET flash memories with split-gate and with an improved inter-poly dielectric (IPD) layer.

Original languageEnglish
Title of host publication2012 IEEE International SOI Conference, SOI 2012
DOIs
Publication statusPublished - 2012 Dec 1
Externally publishedYes
Event2012 IEEE International SOI Conference, SOI 2012 - Napa, CA, United States
Duration: 2012 Oct 12012 Oct 4

Publication series

NameProceedings - IEEE International SOI Conference
ISSN (Print)1078-621X

Other

Other2012 IEEE International SOI Conference, SOI 2012
Country/TerritoryUnited States
CityNapa, CA
Period12/10/112/10/4

ASJC Scopus subject areas

  • Electronic, Optical and Magnetic Materials
  • Electrical and Electronic Engineering

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