Experimental study of physical-vapor-deposited titanium nitride gate with an n+-polycrystalline silicon capping layer and its application to 20nm fin-type double-gate metal-oxide-semiconductor field-effect transistors

Takahiro Kamei, Yongxun Liu, Kazuhiko Endo, Shinichi O'uchi, Junichi Tsukada, Hiromi Yamauchi, Yuki Ishikawa, Tetsuro Hayashida, Takashi Matsukawa, Kunihiro Sakamoto, Atsushi Ogura, Meishoku Masahara

Research output: Contribution to journalArticle

18 Citations (Scopus)

Abstract

We have comparatively investigated the electrical characteristics including threshold voltage (Vth) variability and mobility by fabricating n+polycrystalline silicon (poly-Si) gate and physical-vapor-deposited (PVD) titanium nitride (TiN) gate fin-type double-gate metal-oxide- semiconductor field-effect transistors (FinFETs), and demonstrated 20-nm-thick PVD-TiN gate FinFETs with a symmetrical Vth. It is experimentally found that the gate stack of a 20-nm-thick PVD-TiN layer capped with a 100-nm-thick n+-poly-Si layer is very effective for setting a symmetrical Vth for undoped FinFETs keeping almost the same V th variability and mobility as those in the case of the n +-poly-Si gate only. On the other hand, mobility degradation was observed in the case of pure 50-nm-thick PVD-TiN gates. These results indicate that mobility degradation probably caused by the thick metal gate induced mechanical stress can be effectively suppressed by reducing the PVD-TiN thickness to 20nm or less.

Original languageEnglish
Article number04DC14
JournalJapanese journal of applied physics
Volume50
Issue number4 PART 2
DOIs
Publication statusPublished - 2011 Apr 1
Externally publishedYes

ASJC Scopus subject areas

  • Engineering(all)
  • Physics and Astronomy(all)

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