Experimental operation of an RS flip-flop composed of nonlatching Josephson gates

Yoshinao Mizugaki; Takeshi Onomi; Koji Nakajima; Tsutomu Yamashita

doi:10.1109/77.506689

Experimental operation of an RS flip-flop composed of nonlatching Josephson gates

Yoshinao Mizugaki, Takeshi Onomi, Koji Nakajima, Tsutomu Yamashita

Research Institute of Electrical Communication (RIEC)

Research output: Contribution to journal › Article › peer-review

5 Citations (Scopus)

Abstract

We present the experimental implementation of an RS flip-flop (RS-FF) composed of dc-biased coupled-SQUID (C-SQUID) gates. The C-SQUID gate is a combination of a single-junction SQUID and a double-junction SQUID. This gate utilizes nonhysteretic Josephson functions and it is operated in nonlatching mode with dc-biasing. Several logical functions are able to be realized with a C-SQUID gate by adjusting the input bias and the input signal levels. The speed performance of the gate is evaluated by simulation for ring oscillators, and the minimum switching delay of 65 ps/stage is obtained under Josephson critical current density of 10 kA/cm². We have fabricated the RS-FF composed of two C-SQUID NOR gates. The circuit is integrated using a Nb/AlO_x/Nb junction technology and its operation is demonstrated experimentally.

Original language	English
Pages (from-to)	90-93
Number of pages	4
Journal	IEEE Transactions on Applied Superconductivity
Volume	6
Issue number	2
DOIs	https://doi.org/10.1109/77.506689
Publication status	Published - 1996 Jun 1

ASJC Scopus subject areas

Electronic, Optical and Magnetic Materials
Condensed Matter Physics
Electrical and Electronic Engineering

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abstract = "We present the experimental implementation of an RS flip-flop (RS-FF) composed of dc-biased coupled-SQUID (C-SQUID) gates. The C-SQUID gate is a combination of a single-junction SQUID and a double-junction SQUID. This gate utilizes nonhysteretic Josephson functions and it is operated in nonlatching mode with dc-biasing. Several logical functions are able to be realized with a C-SQUID gate by adjusting the input bias and the input signal levels. The speed performance of the gate is evaluated by simulation for ring oscillators, and the minimum switching delay of 65 ps/stage is obtained under Josephson critical current density of 10 kA/cm2. We have fabricated the RS-FF composed of two C-SQUID NOR gates. The circuit is integrated using a Nb/AlOx/Nb junction technology and its operation is demonstrated experimentally.",

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AU - Mizugaki, Yoshinao

AU - Onomi, Takeshi

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N2 - We present the experimental implementation of an RS flip-flop (RS-FF) composed of dc-biased coupled-SQUID (C-SQUID) gates. The C-SQUID gate is a combination of a single-junction SQUID and a double-junction SQUID. This gate utilizes nonhysteretic Josephson functions and it is operated in nonlatching mode with dc-biasing. Several logical functions are able to be realized with a C-SQUID gate by adjusting the input bias and the input signal levels. The speed performance of the gate is evaluated by simulation for ring oscillators, and the minimum switching delay of 65 ps/stage is obtained under Josephson critical current density of 10 kA/cm2. We have fabricated the RS-FF composed of two C-SQUID NOR gates. The circuit is integrated using a Nb/AlOx/Nb junction technology and its operation is demonstrated experimentally.

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