Experimental 2-bit/cell storage DRAM for macro cell or memory-on-logic application.

Tohru Furuyama, Takashi Ohsawa, Yousei Nagahama, Hiroto Tanaka, Yohji Watanabe, Tohru Kimura, Kazuyoshi Muraoka, Kenji Natori

    Research output: Contribution to journalConference articlepeer-review

    1 Citation (Scopus)


    A novel multiple-level storage DRAM (dynamic random-access memory) technique which obtains fairly fast access time is presented. The RAM area, especially the cell-array area, which is highly defect-sensitive, is reduced with this technique. Reasonable yield can thus be achieved. An experimental 1-Mb DRAM has been fabricated, and the 2-bit/cell storage technique has been verified to be suitable for macro-cell or memory-on-logic application.

    Original languageEnglish
    Pages (from-to)4.4/1-4
    JournalProceedings of the Custom Integrated Circuits Conference
    Publication statusPublished - 1988 Dec 1

    ASJC Scopus subject areas

    • Electrical and Electronic Engineering

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