## Abstract

This paper presents an efficient graph-based evolutionary optimization technique called Evolutionary Graph Generation (EGG), and its application to the design of fast constant-coefficient multipliers using parallel counter-tree architecture. An important feature of EGG is its capability to handle the general graph structures directly in evolution process instead of encoding the graph structures into indirect representations, such as bit strings and trees. This paper also addresses the major problem of EGG regarding the significant computation time required for verifying the function of generated circuits. To solve this problem, a new functional verification technique for arithmetic circuits is proposed. It is demonstrated that the EGG system can create efficient multiplier structures which are comparable or superior to the known conventional designs.

Original language | English |
---|---|

Pages (from-to) | 1767-1777 |

Number of pages | 11 |

Journal | IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences |

Volume | E83-A |

Issue number | 9 |

Publication status | Published - 2000 Jan 1 |

## Keywords

- Arithmetic circuits
- Circuit design
- Computer arithmetic
- Evaluable hardware
- Evolutionary computation

## ASJC Scopus subject areas

- Signal Processing
- Computer Graphics and Computer-Aided Design
- Electrical and Electronic Engineering
- Applied Mathematics