Evolutionary synthesis of arithmetic circuit structures

Takafumi Aoki, Naofumi Homma, Tatsuo Higuchi

Research output: Contribution to journalArticlepeer-review

13 Citations (Scopus)


This paper presents an efficient graph-based evolutionary optimization technique called Evolutionary Graph Generation (EGG), and its application to arithmetic circuit synthesis. Key features of EGG are to employ a graph-based representation of individuals and to manipulate the graph structures directly by evolutionary operations. The potential capability of EGG is demonstrated through experimental synthesis of arithmetic circuits with different levels of abstraction. Design examples include (i) combinational multipliers using world-level arithmetic components (such as parallel counters and parallel shifters), (ii) bit-serial multipliers using bit-level arithmetic components (such as 1-bit full adders and 1-bit registers), and (iii) multiple-valued current-mode arithmetic circuits using transistor-level components (such as current sources and current mirrors).

Original languageEnglish
Pages (from-to)199-232
Number of pages34
JournalArtificial Intelligence Review
Issue number3-4
Publication statusPublished - 2003 Dec 1


  • Arithmetic circuits
  • Circuit design
  • Evolutionary computation
  • Evolutionary design
  • Genetic algorithms
  • Genetic programming
  • Multiple-valued logic

ASJC Scopus subject areas

  • Language and Linguistics
  • Linguistics and Language
  • Artificial Intelligence


Dive into the research topics of 'Evolutionary synthesis of arithmetic circuit structures'. Together they form a unique fingerprint.

Cite this