Evolutionary graph generation with terminal-colour constraint for heterogeneous circuit synthesis

M. Natsui, T. Aoki, T. Higuchi

Research output: Contribution to journalArticlepeer-review

5 Citations (Scopus)

Abstract

A novel graph-based evolutionary optimisation technique that can be used to synthesise heterogeneous circuits consisting of various different components is proposed. The key idea is to introduce 'circuit graphs with coloured terminals' for modelling heterogeneous architectures. The potential of the proposed approach is demonstrated through experimental synthesis of a radix-4 signed-digit (SD) full adder circuit.

Original languageEnglish
Pages (from-to)808-810
Number of pages3
JournalElectronics Letters
Volume37
Issue number13
DOIs
Publication statusPublished - 2001 Jun 21

ASJC Scopus subject areas

  • Electrical and Electronic Engineering

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