Evolutionary graph generation system with terminal-color constraint - An application to multiple-valued logic circuit synthesis -

Research output: Contribution to journalLetterpeer-review

2 Citations (Scopus)

Abstract

This letter presents an efficient graph-based evolutionary optimization technique, and its application to the transistor-level design of multiple-valued arithmetic circuits. The key idea is to introduce "circuit graphs with colored terminals" for modeling heterogeneous networks of various components. The potential of the proposed approach is demonstrated through experimental synthesis of a radix-4 signed-digit (SD) full adder circuit.

Original languageEnglish
Pages (from-to)2808-2810
Number of pages3
JournalIEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences
VolumeE84-A
Issue number11
Publication statusPublished - 2001 Nov

Keywords

  • Arithmetic circuits
  • Evolutionary computation
  • Genetic algorithms
  • Multiple-valued logic

ASJC Scopus subject areas

  • Signal Processing
  • Computer Graphics and Computer-Aided Design
  • Electrical and Electronic Engineering
  • Applied Mathematics

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