Evolutionary graph generation system with symbolic verification for arithmetic circuit design

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13 Citations (Scopus)

Abstract

A novel graph-based evolutionary optimisation technique for arithmetic circuit synthesis is proposed. Symbolic verification of the generated circuit structures is introduced to accelerate the time-consuming evolution process. The evolutionary graph generation (EGG) system based on the proposed technique can successfully generate the optimal 16-bit constant-coefficient multiplier within ∼2.2h.

Original languageEnglish
Pages (from-to)937-939
Number of pages3
JournalElectronics Letters
Volume36
Issue number11
DOIs
Publication statusPublished - 2000 May 25

ASJC Scopus subject areas

  • Electrical and Electronic Engineering

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