Evaluation of the hierarchical temporal memory as soft computing platform and its VLSI architecture

Wim J C Melis, Shuhei Chizuwa, Michitaka Kameyama

Research output: Chapter in Book/Report/Conference proceedingConference contribution

10 Citations (Scopus)

Abstract

A large number of real world applications, like user support systems, can still not be performed easily by conventional algorithms in comparison with the human brain. Recently, such intelligence has often been reached by using probability based systems. This paper presents results on the implementation of one such user support system namely an intention estimation information appliance system, on a Bayesian Network as well as Hierarchical Temporal Memory. The latter is a new and quite promising soft computing platform modelling the human brain, though currently only available as a software model. A second part of the paper therefore focuses on a possible VLSI architecture for Hierarchical Temporal Memory. Since it models the human brain, communication as well as memory are of high importance for this VLSI architecture.

Original languageEnglish
Title of host publicationProceedings - 39th International Symposium on Multiple-Valued Logic, ISMVL 2009
Pages233-238
Number of pages6
DOIs
Publication statusPublished - 2009 Sep 30
Event39th International Symposium on Multiple-Valued Logic, ISMVL 2009 - Naha, Okinawa, Japan
Duration: 2009 May 212009 May 23

Publication series

NameProceedings of The International Symposium on Multiple-Valued Logic
ISSN (Print)0195-623X

Other

Other39th International Symposium on Multiple-Valued Logic, ISMVL 2009
CountryJapan
CityNaha, Okinawa
Period09/5/2109/5/23

ASJC Scopus subject areas

  • Computer Science(all)
  • Mathematics(all)

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