Evaluation of the hierarchical temporal memory as soft computing platform and its VLSI architecture

Wim J C Melis; Shuhei Chizuwa; Michitaka Kameyama

doi:10.1109/ISMVL.2009.11

Evaluation of the hierarchical temporal memory as soft computing platform and its VLSI architecture

Wim J C Melis, Shuhei Chizuwa, Michitaka Kameyama

INF - Computer and Mathematical Sciences

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

10 Citations (Scopus)

Abstract

A large number of real world applications, like user support systems, can still not be performed easily by conventional algorithms in comparison with the human brain. Recently, such intelligence has often been reached by using probability based systems. This paper presents results on the implementation of one such user support system namely an intention estimation information appliance system, on a Bayesian Network as well as Hierarchical Temporal Memory. The latter is a new and quite promising soft computing platform modelling the human brain, though currently only available as a software model. A second part of the paper therefore focuses on a possible VLSI architecture for Hierarchical Temporal Memory. Since it models the human brain, communication as well as memory are of high importance for this VLSI architecture.

Original language	English
Title of host publication	Proceedings - 39th International Symposium on Multiple-Valued Logic, ISMVL 2009
Pages	233-238
Number of pages	6
DOIs	https://doi.org/10.1109/ISMVL.2009.11
Publication status	Published - 2009 Sep 30
Event	39th International Symposium on Multiple-Valued Logic, ISMVL 2009 - Naha, Okinawa, Japan Duration: 2009 May 21 → 2009 May 23

Publication series

Name	Proceedings of The International Symposium on Multiple-Valued Logic
ISSN (Print)	0195-623X

Other

Other	39th International Symposium on Multiple-Valued Logic, ISMVL 2009
Country/Territory	Japan
City	Naha, Okinawa
Period	09/5/21 → 09/5/23

ASJC Scopus subject areas

Computer Science(all)
Mathematics(all)

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10.1109/ISMVL.2009.11

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Melis, W. J. C., Chizuwa, S., & Kameyama, M. (2009). Evaluation of the hierarchical temporal memory as soft computing platform and its VLSI architecture. In Proceedings - 39th International Symposium on Multiple-Valued Logic, ISMVL 2009 (pp. 233-238). [5010405] (Proceedings of The International Symposium on Multiple-Valued Logic). https://doi.org/10.1109/ISMVL.2009.11

Evaluation of the hierarchical temporal memory as soft computing platform and its VLSI architecture. / Melis, Wim J C; Chizuwa, Shuhei; Kameyama, Michitaka.

Proceedings - 39th International Symposium on Multiple-Valued Logic, ISMVL 2009. 2009. p. 233-238 5010405 (Proceedings of The International Symposium on Multiple-Valued Logic).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Melis, WJC, Chizuwa, S & Kameyama, M 2009, Evaluation of the hierarchical temporal memory as soft computing platform and its VLSI architecture. in Proceedings - 39th International Symposium on Multiple-Valued Logic, ISMVL 2009., 5010405, Proceedings of The International Symposium on Multiple-Valued Logic, pp. 233-238, 39th International Symposium on Multiple-Valued Logic, ISMVL 2009, Naha, Okinawa, Japan, 09/5/21. https://doi.org/10.1109/ISMVL.2009.11

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Evaluation of the hierarchical temporal memory as soft computing platform and its VLSI architecture

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