Electroplated copper thin films have started to be applied to the Through Silicon Via (TSV) interconnections. Unfortunately, however, the electrical resistivity of the electroplated copper thin films was found to vary drastically comparing with those of the conventional bulk copper. This was because that the films consisted of grains with low crystallographic quality and a lot of porous grain boundaries. In this study, the electroplated copper thin film interconnections were embedded in a silicon substrate to model the TSV structure. It was observed that many voids and hillocks appeared on the surface of the films after annealed at 400°C. In addition, it was also found that the electrical resistivity of the films without annealing was much higher than that of bulk copper. As a result, it is very important to evaluate the crystallographic quality of the electroplated copper thin films after electroplated to assure the long-term reliability.