Evaluation of shared DRAM for parallel processor system with shared memory

Hiroyuki Kurino, Keiichi Hirano, Taizo Ono, Mitsumasa Koyanagi

Research output: Contribution to journalArticlepeer-review

3 Citations (Scopus)

Abstract

We describe a new multiport memory which is called Shared DRAM (SHDRAM) to overcome bus-bottle neck problem in parallel processor system with shared memory. The processors are directly connected to this SHDRAM without conventional common bus. The test chip with 32kbit memory cells is fabricated using a 1.5 μm CMOS technology. The basic operation is confirmed by the circuit simulation and experimental results. In addition, it is confirmed by the computer simulation that the system performance with SHDRAM is superior to that with conventional common buses.

Original languageEnglish
Pages (from-to)2655-2660
Number of pages6
JournalIEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences
VolumeE81-A
Issue number12
Publication statusPublished - 1998 Jan 1

Keywords

  • DRAM
  • Multiport memory
  • Parallel processor system
  • Shared memory

ASJC Scopus subject areas

  • Signal Processing
  • Computer Graphics and Computer-Aided Design
  • Electrical and Electronic Engineering
  • Applied Mathematics

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