In this study, the impact of plasma stress during TSV (Through Silicon Via) formation process on the device characteristics is investigated. In the TSV formation process, there are several plasma assisted processes such as etching, metal/insulator deposition, ashing and so on, and the devices are exposed to the ambient plasma during these processes. To evaluate the plasma damage, we prepared TEG (Test Element Group) wafers which contain two types of MOSFET; P-Channel MOS and N-Channel MOS, and the TEG wafers include the variation of the gate length and the gate width. We performed TSV process on the TEG wafers including support wafer bonding, TSV wet etching, insulator formation, insulator etching, backside metal formation and passivation formation. After the TSV formation processes, significant threshold voltage shift ΔVth was observed in both types of MOSFET. By conducting additional annealing process, the amount of Vth shift decreased, which implies that the Vth shift occurred because of the defects in the gate oxide induced by the trapped charges in the gate electrode. We also attempted a damage reduction method. In this process, the electrode pads of MOSFET (gate, source, drain and substrate) of each device were electrically connected during the TSV process. After the TSV process, no Vth shift was observed because plasma charges can disperse into the substrate through the connected metal line.