TY - GEN
T1 - Evaluation of plasma process damage during TSV formation and damage reduction method
AU - Igarashi, Takatoshi
AU - Kojima, Kazuaki
AU - Matsumoto, Kazuya
AU - Fujimori, Noriyuki
AU - Nakamura, Tsutomu
N1 - Publisher Copyright:
© 2015 The Japan Institute of Electronics Packaging.
PY - 2015/5/20
Y1 - 2015/5/20
N2 - In this study, the impact of plasma stress during TSV (Through Silicon Via) formation process on the device characteristics is investigated. In the TSV formation process, there are several plasma assisted processes such as etching, metal/insulator deposition, ashing and so on, and the devices are exposed to the ambient plasma during these processes. To evaluate the plasma damage, we prepared TEG (Test Element Group) wafers which contain two types of MOSFET; P-Channel MOS and N-Channel MOS, and the TEG wafers include the variation of the gate length and the gate width. We performed TSV process on the TEG wafers including support wafer bonding, TSV wet etching, insulator formation, insulator etching, backside metal formation and passivation formation. After the TSV formation processes, significant threshold voltage shift ΔVth was observed in both types of MOSFET. By conducting additional annealing process, the amount of Vth shift decreased, which implies that the Vth shift occurred because of the defects in the gate oxide induced by the trapped charges in the gate electrode. We also attempted a damage reduction method. In this process, the electrode pads of MOSFET (gate, source, drain and substrate) of each device were electrically connected during the TSV process. After the TSV process, no Vth shift was observed because plasma charges can disperse into the substrate through the connected metal line.
AB - In this study, the impact of plasma stress during TSV (Through Silicon Via) formation process on the device characteristics is investigated. In the TSV formation process, there are several plasma assisted processes such as etching, metal/insulator deposition, ashing and so on, and the devices are exposed to the ambient plasma during these processes. To evaluate the plasma damage, we prepared TEG (Test Element Group) wafers which contain two types of MOSFET; P-Channel MOS and N-Channel MOS, and the TEG wafers include the variation of the gate length and the gate width. We performed TSV process on the TEG wafers including support wafer bonding, TSV wet etching, insulator formation, insulator etching, backside metal formation and passivation formation. After the TSV formation processes, significant threshold voltage shift ΔVth was observed in both types of MOSFET. By conducting additional annealing process, the amount of Vth shift decreased, which implies that the Vth shift occurred because of the defects in the gate oxide induced by the trapped charges in the gate electrode. We also attempted a damage reduction method. In this process, the electrode pads of MOSFET (gate, source, drain and substrate) of each device were electrically connected during the TSV process. After the TSV process, no Vth shift was observed because plasma charges can disperse into the substrate through the connected metal line.
KW - Plasma process damage
KW - TSV
KW - WL-CSP
UR - http://www.scopus.com/inward/record.url?scp=84936071231&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=84936071231&partnerID=8YFLogxK
U2 - 10.1109/ICEP-IAAC.2015.7111004
DO - 10.1109/ICEP-IAAC.2015.7111004
M3 - Conference contribution
AN - SCOPUS:84936071231
T3 - ICEP-IAAC 2015 - 2015 International Conference on Electronic Packaging and iMAPS All Asia Conference
SP - 74
EP - 77
BT - ICEP-IAAC 2015 - 2015 International Conference on Electronic Packaging and iMAPS All Asia Conference
PB - Institute of Electrical and Electronics Engineers Inc.
T2 - 2015 International Conference on Electronic Packaging and iMAPS All Asia Conference, ICEP-IAAC 2015
Y2 - 14 April 2015 through 17 April 2015
ER -