Evaluation of Cu diffusion from Cu through-silicon via (TSV) in three-dimensional LSI by transient capacitance measurement

Jichel Bea, Kangwook Lee, Takafumi Fukushima, Tetsu Tanaka, Mitsumasa Koyanagi

Research output: Contribution to journalArticlepeer-review

38 Citations (Scopus)

Abstract

The influence of Cu contamination from Cu through-silicon via (TSV) on device reliability in the 3-D LSI has been electrically evaluated by capacitancetime (C-t) measurement. The Cu/Ta gate trench capacitors with two types of Ta barrier layers of 10- and 100-nm thicknesses (at the surface) were fabricated. The C-t curves of the trench capacitors with 100-nm-thick Ta layer exhibit no change after annealing up to 60 min at 300 °C. However, the C-t curves of the trench capacitors with 10-nm-thick Ta layer were severely degraded even after the initial annealing for 5 min. It means that Cu atoms diffuse into the active area from the Cu TSV through scallop portions with extremely thin Ta layer in TSVs, and consequently, the generation lifetime of minority carrier is significantly reduced. The C-t analysis is a useful method to electrically characterize the influence of Cu contamination from the Cu TSV on device reliability in fabricated LSI wafers.

Original languageEnglish
Article number5771041
Pages (from-to)940-942
Number of pages3
JournalIEEE Electron Device Letters
Volume32
Issue number7
DOIs
Publication statusPublished - 2011 Jul

Keywords

  • 3-D LSI
  • Capacitancetime C-t
  • Cu diffusion
  • Cu through-silicon via (TSV)
  • charge carrier lifetime

ASJC Scopus subject areas

  • Electronic, Optical and Magnetic Materials
  • Electrical and Electronic Engineering

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