Evaluation of Cu contamination at backside surface of thinned wafer in 3-D integration by transient-capacitance measurement

Jichel Bea, Kangwook Lee, Takafumi Fukushima, Tetsu Tanaka, Mitsumasa Koyanagi

Research output: Contribution to journalArticle

32 Citations (Scopus)

Abstract

The influence of Cu contamination at backside surface of a thinned wafer in three-dimensional LSI was electrically evaluated by capacitancetime (C t) measurement. A MOS capacitor was fabricated using a thinned wafer of 50-μm thickness. The (Ct) curves of the MOS capacitor were severely degraded even after initial annealing at 300 °C for 5 min. It means that Cu atoms at the back surface reach the Si-SiO2 interface of the front surface, and the generation lifetime is significantly reduced. The quantitative relationship between the generation lifetime and surface concentration of Cu atom was evaluated. The (C t) measurement is a highly promising method to electrically characterize the influence of Cu contamination on device reliability in fabricated LSI wafers.

Original languageEnglish
Article number5640641
Pages (from-to)66-68
Number of pages3
JournalIEEE Electron Device Letters
Volume32
Issue number1
DOIs
Publication statusPublished - 2011 Jan 1

Keywords

  • Capacitancetime (C =t)
  • Cu diffusion
  • charge carrier lifetime
  • three-dimensional (3-D) LSI

ASJC Scopus subject areas

  • Electronic, Optical and Magnetic Materials
  • Electrical and Electronic Engineering

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